mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement SQSHL (register)'s scalar variant

Browse source 
We can implement this in terms of the vector variant.
This commit is contained in:
Lioncash 2019-03-04 14:15:02 -05:00 committed by MerryMage
parent 36027ebef5
commit 35ddf68ad5
2 changed files with 12 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -490,7 +490,7 @@ INST(SQSUB_1, "SQSUB", "01011
INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
INST(SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd")
//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")
INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")

11
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -320,6 +320,17 @@ bool TranslatorVisitor::FCMGT_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return ScalarFPCompareRegister(*this, sz, Vm, Vn, Vd, FPComparisonType::GT);
}
bool TranslatorVisitor::SQSHL_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = 8U << size.ZeroExtend();
const IR::U128 operand1 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0));
const IR::U128 operand2 = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vm), 0));
const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand1, operand2);
ir.SetQ(Vd, result);
return true;
}
bool TranslatorVisitor::SRSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return RoundingShiftLeft(*this, size, Vm, Vn, Vd, Signedness::Signed);
}