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A64: Implement half-precision vector variant of FRECPE

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Lioncash 2019-04-13 19:07:53 -04:00 committed by MerryMage
parent 0945a491bd
commit 3739d92097
2 changed files with 12 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -650,7 +650,7 @@ INST(FCVTPS_4, "FCVTPS (vector)", "0Q001
//INST(FCVTZS_int_3, "FCVTZS (vector, integer)", "0Q00111011111001101110nnnnnddddd")
INST(FCVTZS_int_4, "FCVTZS (vector, integer)", "0Q0011101z100001101110nnnnnddddd")
INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd")
//INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd")
INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd")
INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")

11
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -518,6 +518,17 @@ bool TranslatorVisitor::FRINTI_2(bool Q, bool sz, Vec Vn, Vec Vd) {
return FloatRoundToIntegral(*this, Q, sz, Vn, Vd,ir.current_location->FPCR().RMode(), false);
}
bool TranslatorVisitor::FRECPE_3(bool Q, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
const size_t esize = 16;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.FPVectorRecipEstimate(esize, operand);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FRECPE_4(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();