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ir: Add opcodes for converting S64 and U64 to double-precision values

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Lioncash 2018-07-09 17:14:00 -04:00 committed by MerryMage
parent 436ca80bcd
commit 3a41465eaf
4 changed files with 49 additions and 0 deletions
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35
src/backend_x64/emit_x64_floating_point.cpp
View file

@ -1055,6 +1055,19 @@ void EmitX64::EmitFPS32ToDouble(EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, to);
}
void EmitX64::EmitFPS64ToDouble(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
const bool round_to_nearest = args[1].GetImmediateU1();
ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
code.cvtsi2sd(result, from);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitX64::EmitFPU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
@ -1069,4 +1082,26 @@ void EmitX64::EmitFPU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, to);
}
void EmitX64::EmitFPU64ToDouble(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Reg64 from = ctx.reg_alloc.UseGpr(args[0]);
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
const bool round_to_nearest = args[1].GetImmediateU1();
ASSERT_MSG(!round_to_nearest, "round_to_nearest unimplemented");
if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX512F)) {
code.vcvtusi2sd(result, result, from);
} else {
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
code.movq(tmp, from);
code.punpckldq(tmp, code.MConst(xword, 0x4530000043300000, 0));
code.subpd(tmp, code.MConst(xword, 0x4330000000000000, 0x4530000000000000));
code.pshufd(result, tmp, 0b01001110);
code.addpd(result, tmp);
}
ctx.reg_alloc.DefineValue(inst, result);
}
} // namespace Dynarmic::BackendX64

10
src/frontend/ir/ir_emitter.cpp
View file

@ -1476,6 +1476,11 @@ U32 IREmitter::FPS32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_con
return Inst<U32>(Opcode::FPS32ToSingle, a, Imm1(round_to_nearest));
}
U64 IREmitter::FPS64ToDouble(const U64& a, bool round_to_nearest, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
return Inst<U64>(Opcode::FPS64ToDouble, a, Imm1(round_to_nearest));
}
U32 IREmitter::FPU32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
return Inst<U32>(Opcode::FPU32ToSingle, a, Imm1(round_to_nearest));
@ -1491,6 +1496,11 @@ U64 IREmitter::FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_con
return Inst<U64>(Opcode::FPU32ToDouble, a, Imm1(round_to_nearest));
}
U64 IREmitter::FPU64ToDouble(const U64& a, bool round_to_nearest, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
return Inst<U64>(Opcode::FPU64ToDouble, a, Imm1(round_to_nearest));
}
U128 IREmitter::FPVectorAbs(size_t esize, const U128& a) {
switch (esize) {
case 16:

2
src/frontend/ir/ir_emitter.h
View file

@ -271,7 +271,9 @@ public:
U32 FPS32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U32 FPU32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPS64ToDouble(const U64& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPU32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);
U64 FPU64ToDouble(const U64& a, bool round_to_nearest, bool fpscr_controlled);
U128 FPVectorAbs(size_t esize, const U128& a);
U128 FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b);

2
src/frontend/ir/opcodes.inc
View file

@ -393,7 +393,9 @@ OPCODE(FPDoubleToS32, T::U32, T::U64, T::U
OPCODE(FPU32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPS32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPU32ToDouble, T::U64, T::U32, T::U1 )
OPCODE(FPU64ToDouble, T::U64, T::U64, T::U1 )
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
OPCODE(FPS64ToDouble, T::U64, T::U64, T::U1 )
// Floating-point vector instructions
OPCODE(FPVectorAbs16, T::U128, T::U128 )