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A64: Implement scalar variant of NEG

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Lioncash 2018-04-15 07:19:07 -04:00 committed by MerryMage
parent b4f3051e4b
commit 3ad4e547e4
2 changed files with 13 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -416,7 +416,7 @@ INST(UCVTF_int_2, "UCVTF (vector, integer)", "01111
//INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd") //INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd")
//INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd") //INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd")
//INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd") //INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd")
//INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd") INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd")
//INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd") //INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd")
//INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd") //INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd")
//INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd") //INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd")

12
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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@ -8,6 +8,18 @@
namespace Dynarmic::A64 { namespace Dynarmic::A64 {
bool TranslatorVisitor::NEG_1(Imm<2> size, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();
}
const IR::U64 operand = V_scalar(64, Vn);
const IR::U64 result = ir.Sub(ir.Imm64(0), operand);
V_scalar(64, Vd, result);
return true;
}
bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
const auto esize = sz ? 64 : 32; const auto esize = sz ? 64 : 32;