emit_x64_floating_point: Hardware FMA implementation of FPRSqrtStepFused
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344ee76aba
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3 changed files with 76 additions and 3 deletions
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@ -873,8 +873,58 @@ void EmitX64::EmitFPRSqrtEstimate64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPRSqrtEstimate<u64>(code, ctx, inst);
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}
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template<typename FPT>
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template<size_t fsize>
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static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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using FPT = mp::unsigned_integer_of_size<fsize>;
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Xbyak::Label end, fallback;
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const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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code.vmovaps(result, code.MConst(xword, FP::FPValue<FPT, false, 0, 3>()));
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FCODE(vfnmadd231s)(result, operand1, operand2);
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// Detect if the intermediate result is infinity or NaN or nearly an infinity.
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// Why do we need to care about infinities? This is because x86 doesn't allow us
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// to fuse the divide-by-two with the rest of the FMA operation. Therefore the
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// intermediate value may overflow and we would like to handle this case.
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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code.vpextrw(tmp, result, fsize == 32 ? 1 : 3);
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code.and_(tmp.cvt16(), fsize == 32 ? 0x7f80 : 0x7ff0);
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code.cmp(tmp.cvt16(), fsize == 32 ? 0x7f00 : 0x7fe0);
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ctx.reg_alloc.Release(tmp);
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code.jae(fallback, code.T_NEAR);
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FCODE(vmuls)(result, result, code.MConst(xword, FP::FPValue<FPT, false, -1, 1>()));
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code.L(end);
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code.SwitchToFarCode();
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code.L(fallback);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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code.movq(code.ABI_PARAM1, operand1);
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code.movq(code.ABI_PARAM2, operand2);
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code.mov(code.ABI_PARAM3.cvt32(), ctx.FPCR());
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code.lea(code.ABI_PARAM4, code.ptr[code.r15 + code.GetJitStateInfo().offsetof_fpsr_exc]);
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code.CallFunction(&FP::FPRSqrtStepFused<FPT>);
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code.movq(result, code.ABI_RETURN);
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ctx.reg_alloc.HostCall(inst, args[0], args[1]);
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code.mov(code.ABI_PARAM3.cvt32(), ctx.FPCR());
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@ -883,11 +933,11 @@ static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
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}
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void EmitX64::EmitFPRSqrtStepFused32(EmitContext& ctx, IR::Inst* inst) {
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EmitFPRSqrtStepFused<u32>(code, ctx, inst);
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EmitFPRSqrtStepFused<32>(code, ctx, inst);
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}
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void EmitX64::EmitFPRSqrtStepFused64(EmitContext& ctx, IR::Inst* inst) {
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EmitFPRSqrtStepFused<u64>(code, ctx, inst);
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EmitFPRSqrtStepFused<64>(code, ctx, inst);
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}
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void EmitX64::EmitFPSqrt32(EmitContext& ctx, IR::Inst* inst) {
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@ -472,3 +472,25 @@ TEST_CASE("A64: FNEG failed to zero upper", "[a64]") {
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REQUIRE(jit.GetVector(28) == Vector{0x79ee7a03980db670, 0});
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REQUIRE(FP::FPSR{jit.GetFpsr()}.QC() == false);
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}
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TEST_CASE("A64: FRSQRTS", "[a64]") {
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A64TestEnv env;
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Dynarmic::A64::Jit jit{Dynarmic::A64::UserConfig{&env}};
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env.code_mem.emplace_back(0x5eb8fcad); // FRSQRTS S13, S5, S24
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env.code_mem.emplace_back(0x14000000); // B .
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// These particular values result in an intermediate value during
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// the calculation that is close to infinity. We want to verify
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// that this special case is handled appropriately.
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jit.SetPC(0);
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jit.SetVector(5, {0xfc6a0206, 0});
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jit.SetVector(24, {0xfc6a0206, 0});
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jit.SetFpcr(0x00400000);
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env.ticks_left = 2;
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jit.Run();
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REQUIRE(jit.GetVector(13) == Vector{0xff7fffff, 0});
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}
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@ -13,3 +13,4 @@ static_assert(FPValue<u32, false, -1, 3>() == 0x3fc00000);
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static_assert(FPValue<u32, false, 0, 12739812>() == 0x4b4264e4);
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static_assert(FPValue<u32, false, -8, 100>() == 0x3ec80000);
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static_assert(FPValue<u32, true, 0, 1>() == 0xbf800000);
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static_assert(FPValue<u32, false, -1, 1>() == 0x3f000000);
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