A64: Implement DUP (general)
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793753bf63
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3caf192f60
4 changed files with 54 additions and 1 deletions
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@ -75,6 +75,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/load_store_register_immediate.cpp
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frontend/A64/translate/impl/load_store_register_pair.cpp
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frontend/A64/translate/impl/move_wide.cpp
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frontend/A64/translate/impl/simd_copy.cpp
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frontend/A64/translate/impl/simd_three_same.cpp
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frontend/A64/translate/impl/system.cpp
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frontend/A64/translate/translate.cpp
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@ -98,6 +98,17 @@ inline int HighestSetBit(T value) {
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return result;
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}
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template <typename T>
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inline size_t LowestSetBit(T value) {
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auto x = static_cast<std::make_unsigned_t<T>>(value);
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size_t result = 0;
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while ((x & 1) == 0) {
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x >>= 1;
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result++;
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}
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return result;
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}
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template <typename T>
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inline T Ones(size_t count) {
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ASSERT_MSG(count <= BitSize<T>(), "count larger than bitsize of T");
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@ -689,7 +689,7 @@ INST(ADD_vector, "ADD (vector)", "0Q001
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//INST(EXT, "EXT", "0Q101110000mmmmm0iiii0nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD Copy
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//INST(DUP_gen, "DUP (general)", "0Q001110000iiiii000011nnnnnddddd")
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INST(DUP_gen, "DUP (general)", "0Q001110000iiiii000011nnnnnddddd")
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//INST(SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd")
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//INST(UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd")
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//INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd")
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41
src/frontend/A64/translate/impl/simd_copy.cpp
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41
src/frontend/A64/translate/impl/simd_copy.cpp
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@ -0,0 +1,41 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "common/bit_util.h"
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic {
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namespace A64 {
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bool TranslatorVisitor::DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) {
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const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
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if (size > 3) return UnallocatedEncoding();
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if (size == 3 && !Q) return ReservedValue();
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const size_t esize = 8 << size;
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const size_t datasize = Q ? 128 : 64;
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const IR::UAny element = X(esize, Rn);
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const IR::U128 result = [&]{
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switch (esize) {
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case 8:
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return Q ? ir.VectorBroadcast8(element) : ir.VectorLowerBroadcast8(element);
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case 16:
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return Q ? ir.VectorBroadcast16(element) : ir.VectorLowerBroadcast16(element);
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case 32:
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return Q ? ir.VectorBroadcast32(element) : ir.VectorLowerBroadcast32(element);
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default:
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return ir.VectorBroadcast64(element);
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}
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}();
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V(datasize, Vd, result);
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return true;
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}
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} // namespace A64
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} // namespace Dynarmic
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