A64: Implement DUP (general)

This commit is contained in:
MerryMage 2018-01-24 12:00:56 +00:00
parent 793753bf63
commit 3caf192f60
4 changed files with 54 additions and 1 deletions

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@ -75,6 +75,7 @@ add_library(dynarmic
frontend/A64/translate/impl/load_store_register_immediate.cpp
frontend/A64/translate/impl/load_store_register_pair.cpp
frontend/A64/translate/impl/move_wide.cpp
frontend/A64/translate/impl/simd_copy.cpp
frontend/A64/translate/impl/simd_three_same.cpp
frontend/A64/translate/impl/system.cpp
frontend/A64/translate/translate.cpp

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@ -98,6 +98,17 @@ inline int HighestSetBit(T value) {
return result;
}
template <typename T>
inline size_t LowestSetBit(T value) {
auto x = static_cast<std::make_unsigned_t<T>>(value);
size_t result = 0;
while ((x & 1) == 0) {
x >>= 1;
result++;
}
return result;
}
template <typename T>
inline T Ones(size_t count) {
ASSERT_MSG(count <= BitSize<T>(), "count larger than bitsize of T");

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@ -689,7 +689,7 @@ INST(ADD_vector, "ADD (vector)", "0Q001
//INST(EXT, "EXT", "0Q101110000mmmmm0iiii0nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Copy
//INST(DUP_gen, "DUP (general)", "0Q001110000iiiii000011nnnnnddddd")
INST(DUP_gen, "DUP (general)", "0Q001110000iiiii000011nnnnnddddd")
//INST(SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd")
//INST(UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd")
//INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd")

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@ -0,0 +1,41 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include "common/bit_util.h"
#include "frontend/A64/translate/impl/impl.h"
namespace Dynarmic {
namespace A64 {
bool TranslatorVisitor::DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) {
const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
if (size > 3) return UnallocatedEncoding();
if (size == 3 && !Q) return ReservedValue();
const size_t esize = 8 << size;
const size_t datasize = Q ? 128 : 64;
const IR::UAny element = X(esize, Rn);
const IR::U128 result = [&]{
switch (esize) {
case 8:
return Q ? ir.VectorBroadcast8(element) : ir.VectorLowerBroadcast8(element);
case 16:
return Q ? ir.VectorBroadcast16(element) : ir.VectorLowerBroadcast16(element);
case 32:
return Q ? ir.VectorBroadcast32(element) : ir.VectorLowerBroadcast32(element);
default:
return ir.VectorBroadcast64(element);
}
}();
V(datasize, Vd, result);
return true;
}
} // namespace A64
} // namespace Dynarmic