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A64: NOP immediate variant of PRFM

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Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
This commit is contained in:
Lioncash 2018-03-29 15:16:23 -04:00 committed by MerryMage
parent e7b60189b3
commit 40ec25356b
2 changed files with 7 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -174,7 +174,7 @@ INST(UnallocatedEncoding, "", "--101
INST(STURx_LDURx, "STURx/LDURx", "zz111000oo0iiiiiiiii00nnnnnttttt") INST(STURx_LDURx, "STURx/LDURx", "zz111000oo0iiiiiiiii00nnnnnttttt")
INST(UnallocatedEncoding, "", "111110001-0---------00----------") INST(UnallocatedEncoding, "", "111110001-0---------00----------")
INST(UnallocatedEncoding, "", "10111000110---------00----------") INST(UnallocatedEncoding, "", "10111000110---------00----------")
//INST(PRFM_imm, "PRFM (immediate)", "1111100110iiiiiiiiiiiinnnnnttttt") INST(PRFM_imm, "PRFM (immediate)", "1111100110iiiiiiiiiiiinnnnnttttt")
INST(STUR_fpsimd, "STUR (SIMD&FP)", "zz111100o00iiiiiiiii00nnnnnttttt") INST(STUR_fpsimd, "STUR (SIMD&FP)", "zz111100o00iiiiiiiii00nnnnnttttt")
INST(LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100o10iiiiiiiii00nnnnnttttt") INST(LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100o10iiiiiiiii00nnnnnttttt")

6
src/frontend/A64/translate/impl/load_store_register_immediate.cpp
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@ -100,6 +100,12 @@ bool TranslatorVisitor::STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn
return load_store_register_immediate(wback, postindex, scale, offset, size, opc, Rn, Rt); return load_store_register_immediate(wback, postindex, scale, offset, size, opc, Rn, Rt);
} }
bool TranslatorVisitor::PRFM_imm([[maybe_unused]] Imm<12> imm12, [[maybe_unused]] Reg Rn, [[maybe_unused]] Reg Rt) {
// Currently a NOP (which is valid behavior, as indicated by
// the ARMv8 architecture reference manual)
return true;
}
static bool LoadStoreSIMD(TranslatorVisitor& tv, IREmitter& ir, bool wback, bool postindex, size_t scale, u64 offset, MemOp memop, Reg Rn, Vec Vt) { static bool LoadStoreSIMD(TranslatorVisitor& tv, IREmitter& ir, bool wback, bool postindex, size_t scale, u64 offset, MemOp memop, Reg Rn, Vec Vt) {
const AccType acctype = AccType::VEC; const AccType acctype = AccType::VEC;
const size_t datasize = 8 << scale; const size_t datasize = 8 << scale;