A64: Implement Load/Store register (unprivileged)
This commit is contained in:
James Rowe
MerryMage
parent
01a26fa644
commit
41e6e659c5
4 changed files with 161 additions and 13 deletions
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@ -74,6 +74,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/load_store_load_literal.cpp
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frontend/A64/translate/impl/load_store_register_immediate.cpp
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frontend/A64/translate/impl/load_store_register_pair.cpp
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frontend/A64/translate/impl/load_store_register_unprivileged.cpp
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frontend/A64/translate/impl/move_wide.cpp
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frontend/A64/translate/impl/simd_copy.cpp
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frontend/A64/translate/impl/simd_three_same.cpp
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@ -214,15 +214,15 @@ INST(LDR_imm_fpsimd_1, "LDR (immediate, SIMD&FP)", "zz111
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INST(LDR_imm_fpsimd_2, "LDR (immediate, SIMD&FP)", "zz111101o1iiiiiiiiiiiinnnnnttttt")
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// Loads and stores - Load/Store register (unprivileged)
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//INST(STTRB, "STTRB", "00111000000iiiiiiiii10nnnnnttttt")
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//INST(LDTRB, "LDTRB", "00111000010iiiiiiiii10nnnnnttttt")
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//INST(LDTRSB, "LDTRSB", "001110001-0iiiiiiiii10nnnnnttttt")
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//INST(STTRH, "STTRH", "01111000000iiiiiiiii10nnnnnttttt")
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//INST(LDTRH, "LDTRH", "01111000010iiiiiiiii10nnnnnttttt")
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//INST(LDTRSH, "LDTRSH", "011110001-0iiiiiiiii10nnnnnttttt")
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//INST(STTR, "STTR", "1-111000000iiiiiiiii10nnnnnttttt")
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//INST(LDTR, "LDTR", "1-111000010iiiiiiiii10nnnnnttttt")
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//INST(LDTRSW, "LDTRSW", "10111000100iiiiiiiii10nnnnnttttt")
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INST(STTRB, "STTRB", "00111000000iiiiiiiii10nnnnnttttt")
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INST(LDTRB, "LDTRB", "00111000010iiiiiiiii10nnnnnttttt")
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INST(LDTRSB, "LDTRSB", "00111000oo0iiiiiiiii10nnnnnttttt")
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INST(STTRH, "STTRH", "01111000000iiiiiiiii10nnnnnttttt")
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INST(LDTRH, "LDTRH", "01111000010iiiiiiiii10nnnnnttttt")
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INST(LDTRSH, "LDTRSH", "011110001-0iiiiiiiii10nnnnnttttt")
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INST(STTR, "STTR", "1z111000000iiiiiiiii10nnnnnttttt")
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INST(LDTR, "LDTR", "1z111000010iiiiiiiii10nnnnnttttt")
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INST(LDTRSW, "LDTRSW", "10111000100iiiiiiiii10nnnnnttttt")
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// Loads and stores - Atomic memory options
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//INST(LDADDB, "LDADDB, LDADDAB, LDADDALB, LDADDLB", "00111000AR1sssss000000nnnnnttttt")
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@ -267,12 +267,12 @@ struct TranslatorVisitor final {
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// Loads and stores - Load/Store register (unprivileged)
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bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRB(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRSB(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRSB(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt);
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bool STTRH(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRH(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRSH(Imm<9> imm9, Reg Rn, Reg Rt);
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bool STTR(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTR(Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRSH(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt);
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bool STTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt);
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bool LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt);
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// Loads and stores - Atomic memory options
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@ -0,0 +1,147 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic {
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namespace A64 {
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static bool store_register(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize, Imm<9> imm9,
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Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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IR::U64 address;
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if (Rn == Reg::SP) {
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// TODO: Check Stack Alignment
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address = tv.SP(datasize);
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} else {
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address = tv.X(datasize, Rn);
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}
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address = ir.Add(address, ir.Imm64(offset));
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IR::UAny data = tv.X(datasize, Rt);
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tv.Mem(address, datasize / 8, acctype, data);
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return true;
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}
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static bool load_register(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize, Imm<9> imm9,
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Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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IR::U64 address;
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if (Rn == Reg::SP) {
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// TODO: Check Stack Alignment
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address = tv.SP(datasize);
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} else {
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address = tv.X(datasize, Rn);
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}
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address = ir.Add(address, ir.Imm64(offset));
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IR::UAny data = tv.Mem(address, datasize / 8, acctype);
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tv.X(datasize, Rt, tv.ZeroExtend(data, 32));
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}
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static bool load_register_signed(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize,
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Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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MemOp memop;
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bool signed_;
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size_t regsize;
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if (opc.Bit<1>() == 0) {
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// store or zero-extending load
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memop = opc.Bit<0>() ? MemOp::LOAD : MemOp::STORE;
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regsize = 32;
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signed_ = false;
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} else {
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// sign-extending load
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memop = MemOp::LOAD;
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regsize = opc.Bit<0>() ? 32 : 64;
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signed_ = true;
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}
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IR::U64 address;
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if (Rn == Reg::SP) {
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// TODO: Check Stack Alignment
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address = tv.SP(datasize);
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} else {
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address = tv.X(datasize, Rn);
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}
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address = ir.Add(address, ir.Imm64(offset));
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switch (memop) {
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case MemOp::STORE:
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tv.Mem(address, datasize / 8, acctype, tv.X(datasize, Rt));
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break;
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case MemOp::LOAD: {
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IR::U8 data = tv.Mem(address, datasize / 8, acctype);
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if (signed_) {
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tv.X(datasize, Rt, tv.SignExtend(data, regsize));
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} else {
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tv.X(datasize, Rt, tv.ZeroExtend(data, regsize));
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}
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break;
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}
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case MemOp::PREFETCH:
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// Prefetch(address, Rt);
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break;
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}
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return true;
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}
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bool TranslatorVisitor::STTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
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return store_register(*this, ir, 8, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::STTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
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return store_register(*this, ir, 16, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::STTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
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const size_t scale = size.ZeroExtend<size_t>();
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const size_t datasize = 8 << scale;
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return store_register(*this, ir, datasize, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register(*this, ir, 8, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register(*this, ir, 16, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
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const size_t scale = size.ZeroExtend<size_t>();
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const size_t datasize = 8 << scale;
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return load_register(*this, ir, datasize, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRSB(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register_signed(*this, ir, 8, opc, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRSH(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register_signed(*this, ir, 16, opc, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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IR::U64 address;
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if (Rn == Reg::SP) {
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// TODO: Check Stack Alignment
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address = SP(32);
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} else {
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address = X(32, Rn);
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}
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address = ir.Add(address, ir.Imm64(offset));
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IR::UAny data = Mem(address, 4, acctype);
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X(32, Rt, SignExtend(data, 64));
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}
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} // namespace A64
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} // namespace Dynarmic
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