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frontend/ir_emitter: Add half-precision opcode for FPVectorEquals

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Lioncash 2019-05-24 19:26:40 -04:00 committed by MerryMage
parent 557a01a787
commit 43fd2b400a
4 changed files with 12 additions and 0 deletions
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8
src/backend/x64/emit_x64_vector_floating_point.cpp
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@ -541,6 +541,14 @@ void EmitX64::EmitFPVectorDiv64(EmitContext& ctx, IR::Inst* inst) {
EmitThreeOpVectorOperation<64, DefaultIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::divpd); EmitThreeOpVectorOperation<64, DefaultIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::divpd);
} }
void EmitX64::EmitFPVectorEqual16(EmitContext& ctx, IR::Inst* inst) {
EmitThreeOpFallback(code, ctx, inst, [](VectorArray<u16>& result, const VectorArray<u16>& op1, const VectorArray<u16>& op2, FP::FPCR fpcr, FP::FPSR& fpsr) {
for (size_t i = 0; i < result.size(); i++) {
result[i] = FP::FPCompareEQ(op1[i], op2[i], fpcr, fpsr) ? 0xFFFF : 0;
}
});
}
void EmitX64::EmitFPVectorEqual32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorEqual32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]); const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);

2
src/frontend/ir/ir_emitter.cpp
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@ -2276,6 +2276,8 @@ U128 IREmitter::FPVectorDiv(size_t esize, const U128& a, const U128& b) {
U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) { U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) {
switch (esize) { switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorEqual16, a, b);
case 32: case 32:
return Inst<U128>(Opcode::FPVectorEqual32, a, b); return Inst<U128>(Opcode::FPVectorEqual32, a, b);
case 64: case 64:

1
src/frontend/ir/microinstruction.cpp
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@ -339,6 +339,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorAdd64: case Opcode::FPVectorAdd64:
case Opcode::FPVectorDiv32: case Opcode::FPVectorDiv32:
case Opcode::FPVectorDiv64: case Opcode::FPVectorDiv64:
case Opcode::FPVectorEqual16:
case Opcode::FPVectorEqual32: case Opcode::FPVectorEqual32:
case Opcode::FPVectorEqual64: case Opcode::FPVectorEqual64:
case Opcode::FPVectorFromSignedFixed32: case Opcode::FPVectorFromSignedFixed32:

1
src/frontend/ir/opcodes.inc
View file

@ -554,6 +554,7 @@ OPCODE(FPVectorAdd32, U128, U128
OPCODE(FPVectorAdd64, U128, U128, U128 ) OPCODE(FPVectorAdd64, U128, U128, U128 )
OPCODE(FPVectorDiv32, U128, U128, U128 ) OPCODE(FPVectorDiv32, U128, U128, U128 )
OPCODE(FPVectorDiv64, U128, U128, U128 ) OPCODE(FPVectorDiv64, U128, U128, U128 )
OPCODE(FPVectorEqual16, U128, U128, U128 )
OPCODE(FPVectorEqual32, U128, U128, U128 ) OPCODE(FPVectorEqual32, U128, U128, U128 )
OPCODE(FPVectorEqual64, U128, U128, U128 ) OPCODE(FPVectorEqual64, U128, U128, U128 )
OPCODE(FPVectorFromSignedFixed32, U128, U128, U8, U8 ) OPCODE(FPVectorFromSignedFixed32, U128, U128, U8, U8 )