A64: Implement FNEG
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db958061a3
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2 changed files with 13 additions and 1 deletions
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@ -909,7 +909,7 @@ INST(FCVTZU_float_int, "FCVTZU (scalar, integer)", "z0011
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// Data Processing - FP and SIMD - Floating point data processing
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//INST(FMOV_float, "FMOV (register)", "00011110yy100000010000nnnnnddddd")
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INST(FABS_float, "FABS (scalar)", "00011110yy100000110000nnnnnddddd")
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//INST(FNEG_float, "FNEG (scalar)", "00011110yy100001010000nnnnnddddd")
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INST(FNEG_float, "FNEG (scalar)", "00011110yy100001010000nnnnnddddd")
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//INST(FSQRT_float, "FSQRT (scalar)", "00011110yy100001110000nnnnnddddd")
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INST(FCVT_float, "FCVT", "00011110yy10001oo10000nnnnnddddd")
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//INST(FRINTN_float, "FRINTN (scalar)", "00011110yy100100010000nnnnnddddd")
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@ -34,6 +34,18 @@ bool TranslatorVisitor::FABS_float(Imm<2> type, Vec Vn, Vec Vd) {
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return true;
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}
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bool TranslatorVisitor::FNEG_float(Imm<2> type, Vec Vn, Vec Vd) {
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boost::optional<size_t> datasize = GetDataSize(type);
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if (!datasize || *datasize == 16) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operand = V_scalar(*datasize, Vn);
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const IR::U32U64 result = ir.FPNeg(operand);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FMOV_float_imm(Imm<2> type, Imm<8> imm8, Vec Vd) {
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boost::optional<size_t> datasize = GetDataSize(type);
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if (!datasize) {
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