mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

frontend/A32: Correct more IT state

Browse source
This commit is contained in:
MerryMage 2021-05-04 16:18:03 +01:00
parent c5f5c1d40f
commit 462c884685
5 changed files with 11 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/frontend/A32/translate/conditional_state.cpp
View file

@ -41,7 +41,7 @@ bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) {
v.cond_state = ConditionalState::Trailing; v.cond_state = ConditionalState::Trailing;
} else { } else {
if (cond == v.ir.block.GetCondition()) { if (cond == v.ir.block.GetCondition()) {
v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(v.current_instruction_size).AdvanceIT()); v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(static_cast<int>(v.current_instruction_size)).AdvanceIT());
v.ir.block.ConditionFailedCycleCount()++; v.ir.block.ConditionFailedCycleCount()++;
return true; return true;
} }
@ -72,7 +72,7 @@ bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) {
v.cond_state = ConditionalState::Translating; v.cond_state = ConditionalState::Translating;
v.ir.block.SetCondition(cond); v.ir.block.SetCondition(cond);
v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(v.current_instruction_size).AdvanceIT()); v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(static_cast<int>(v.current_instruction_size)).AdvanceIT());
v.ir.block.ConditionFailedCycleCount() = v.ir.block.CycleCount() + 1; v.ir.block.ConditionFailedCycleCount() = v.ir.block.CycleCount() + 1;
return true; return true;
} }

4
src/frontend/A32/translate/impl/thumb16.cpp
View file

@ -1002,7 +1002,7 @@ bool TranslatorVisitor::thumb16_BLX_reg(Reg m) {
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
ir.PushRSB(ir.current_location.AdvancePC(2)); ir.PushRSB(ir.current_location.AdvancePC(2).AdvanceIT());
ir.UpdateUpperLocationDescriptor(); ir.UpdateUpperLocationDescriptor();
ir.BXWritePC(ir.GetRegister(m)); ir.BXWritePC(ir.GetRegister(m));
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1)); ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1));
@ -1013,9 +1013,9 @@ bool TranslatorVisitor::thumb16_BLX_reg(Reg m) {
// SVC #<imm8> // SVC #<imm8>
bool TranslatorVisitor::thumb16_SVC(Imm<8> imm8) { bool TranslatorVisitor::thumb16_SVC(Imm<8> imm8) {
const u32 imm32 = imm8.ZeroExtend(); const u32 imm32 = imm8.ZeroExtend();
ir.PushRSB(ir.current_location.AdvancePC(2).AdvanceIT());
ir.UpdateUpperLocationDescriptor(); ir.UpdateUpperLocationDescriptor();
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 2)); ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 2));
ir.PushRSB(ir.current_location.AdvancePC(2));
ir.CallSupervisor(ir.Imm32(imm32)); ir.CallSupervisor(ir.Imm32(imm32));
ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}}); ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
return false; return false;

4
src/frontend/A32/translate/impl/thumb32_branch.cpp
View file

@ -16,7 +16,7 @@ bool TranslatorVisitor::thumb32_BL_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
ir.PushRSB(ir.current_location.AdvancePC(4)); ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT());
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1)); ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
const s32 imm32 = static_cast<s32>((concatenate(S, i1, i2, hi, lo).SignExtend<u32>() << 1) + 4); const s32 imm32 = static_cast<s32>((concatenate(S, i1, i2, hi, lo).SignExtend<u32>() << 1) + 4);
@ -40,7 +40,7 @@ bool TranslatorVisitor::thumb32_BLX_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1>
return UnpredictableInstruction(); return UnpredictableInstruction();
} }
ir.PushRSB(ir.current_location.AdvancePC(4)); ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT());
ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1)); ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
const s32 imm32 = static_cast<s32>(concatenate(S, i1, i2, hi, lo).SignExtend<u32>() << 1); const s32 imm32 = static_cast<s32>(concatenate(S, i1, i2, hi, lo).SignExtend<u32>() << 1);

4
src/frontend/A32/translate/impl/thumb32_control.cpp
View file

@ -93,11 +93,13 @@ bool TranslatorVisitor::thumb32_MSR_reg(bool write_spsr, Reg n, Imm<4> mask) {
ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000))); ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000)));
} }
} else { } else {
ir.UpdateUpperLocationDescriptor();
const u32 cpsr_mask = (write_nzcvq ? 0xF8000000 : 0) | (write_g ? 0x000F0000 : 0) | 0x00000200; const u32 cpsr_mask = (write_nzcvq ? 0xF8000000 : 0) | (write_g ? 0x000F0000 : 0) | 0x00000200;
const auto old_cpsr = ir.And(ir.GetCpsr(), ir.Imm32(~cpsr_mask)); const auto old_cpsr = ir.And(ir.GetCpsr(), ir.Imm32(~cpsr_mask));
const auto new_cpsr = ir.And(value, ir.Imm32(cpsr_mask)); const auto new_cpsr = ir.And(value, ir.Imm32(cpsr_mask));
ir.SetCpsr(ir.Or(old_cpsr, new_cpsr)); ir.SetCpsr(ir.Or(old_cpsr, new_cpsr));
ir.PushRSB(ir.current_location.AdvancePC(4)); ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT());
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4)); ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}}); ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
return false; return false;

3
src/frontend/A32/translate/impl/vfp.cpp
View file

@ -1137,8 +1137,9 @@ bool TranslatorVisitor::vfp_VMSR(Cond cond, Reg t) {
} }
// TODO: Replace this with a local cache. // TODO: Replace this with a local cache.
ir.PushRSB(ir.current_location.AdvancePC(4)); ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT());
ir.UpdateUpperLocationDescriptor();
ir.SetFpscr(ir.GetRegister(t)); ir.SetFpscr(ir.GetRegister(t));
ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4)); ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
ir.SetTerm(IR::Term::PopRSBHint{}); ir.SetTerm(IR::Term::PopRSBHint{});