test_generator: A64
This commit is contained in:
Merry
Liam
parent
21b4211414
commit
46aef36a4f
1 changed files with 241 additions and 34 deletions
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@ -14,6 +14,7 @@
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#include <mcl/stdint.hpp>
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#include "./A32/testenv.h"
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#include "./A64/testenv.h"
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#include "./fuzz_util.h"
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#include "./rand_int.h"
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#include "dynarmic/common/fp/fpcr.h"
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@ -22,7 +23,11 @@
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#include "dynarmic/frontend/A32/a32_location_descriptor.h"
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#include "dynarmic/frontend/A32/a32_types.h"
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#include "dynarmic/frontend/A32/translate/a32_translate.h"
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#include "dynarmic/frontend/A64/a64_location_descriptor.h"
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#include "dynarmic/frontend/A64/a64_types.h"
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#include "dynarmic/frontend/A64/translate/a64_translate.h"
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#include "dynarmic/interface/A32/a32.h"
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#include "dynarmic/interface/A64/a64.h"
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#include "dynarmic/ir/basic_block.h"
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#include "dynarmic/ir/location_descriptor.h"
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#include "dynarmic/ir/opcodes.h"
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@ -36,21 +41,14 @@ constexpr bool mask_fpsr_cum_bits = true;
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namespace {
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using namespace Dynarmic;
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bool ShouldTestInst(u32 instruction, u32 pc, bool is_thumb, bool is_last_inst, A32::ITState it_state = {}) {
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const A32::LocationDescriptor location = A32::LocationDescriptor{pc, {}, {}}.SetTFlag(is_thumb).SetIT(it_state);
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IR::Block block{location};
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const bool should_continue = A32::TranslateSingleInstruction(block, location, instruction);
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if (!should_continue && !is_last_inst) {
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return false;
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}
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bool ShouldTestInst(IR::Block& block) {
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if (auto terminal = block.GetTerminal(); boost::get<IR::Term::Interpret>(&terminal)) {
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return false;
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}
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for (const auto& ir_inst : block) {
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switch (ir_inst.GetOpcode()) {
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// A32
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case IR::Opcode::A32GetFpscr:
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case IR::Opcode::A32ExceptionRaised:
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case IR::Opcode::A32CallSupervisor:
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@ -61,6 +59,11 @@ bool ShouldTestInst(u32 instruction, u32 pc, bool is_thumb, bool is_last_inst, A
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case IR::Opcode::A32CoprocGetTwoWords:
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case IR::Opcode::A32CoprocLoadWords:
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case IR::Opcode::A32CoprocStoreWords:
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// A64
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case IR::Opcode::A64ExceptionRaised:
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case IR::Opcode::A64CallSupervisor:
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case IR::Opcode::A64DataCacheOperationRaised:
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case IR::Opcode::A64GetCNTPCT:
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// Half-precision
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case IR::Opcode::FPVectorAbs16:
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case IR::Opcode::FPVectorEqual16:
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@ -84,6 +87,30 @@ bool ShouldTestInst(u32 instruction, u32 pc, bool is_thumb, bool is_last_inst, A
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return true;
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}
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bool ShouldTestA32Inst(u32 instruction, u32 pc, bool is_thumb, bool is_last_inst, A32::ITState it_state = {}) {
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const A32::LocationDescriptor location = A32::LocationDescriptor{pc, {}, {}}.SetTFlag(is_thumb).SetIT(it_state);
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IR::Block block{location};
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const bool should_continue = A32::TranslateSingleInstruction(block, location, instruction);
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if (!should_continue && !is_last_inst) {
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return false;
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}
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return ShouldTestInst(block);
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}
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bool ShouldTestA64Inst(u32 instruction, u32 pc, bool is_last_inst) {
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const A64::LocationDescriptor location = A64::LocationDescriptor{pc, {}};
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IR::Block block{location};
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const bool should_continue = A64::TranslateSingleInstruction(block, location, instruction);
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if (!should_continue && !is_last_inst) {
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return false;
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}
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return ShouldTestInst(block);
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}
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u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
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static const struct InstructionGeneratorInfo {
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std::vector<InstructionGenerator> generators;
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@ -144,7 +171,7 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
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continue;
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}
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if (ShouldTestInst(inst, pc, false, is_last_inst)) {
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if (ShouldTestA32Inst(inst, pc, false, is_last_inst)) {
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return inst;
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}
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}
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@ -245,7 +272,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
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const u32 inst = instructions.generators[index].Generate();
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const bool is_four_bytes = (inst >> 16) != 0;
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if (ShouldTestInst(is_four_bytes ? mcl::bit::swap_halves_32(inst) : inst, pc, true, is_last_inst, it_state)) {
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if (ShouldTestA32Inst(is_four_bytes ? mcl::bit::swap_halves_32(inst) : inst, pc, true, is_last_inst, it_state)) {
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if (is_four_bytes)
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return {static_cast<u16>(inst >> 16), static_cast<u16>(inst)};
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return {static_cast<u16>(inst)};
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@ -253,8 +280,65 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
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}
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}
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u32 GenRandomA64Inst(u64 pc, bool is_last_inst) {
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static const struct InstructionGeneratorInfo {
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std::vector<InstructionGenerator> generators;
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std::vector<InstructionGenerator> invalid;
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} instructions = [] {
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const std::vector<std::tuple<std::string, const char*>> list{
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#define INST(fn, name, bitstring) {#fn, bitstring},
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#include "dynarmic/frontend/A64/decoder/a64.inc"
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#undef INST
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};
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std::vector<InstructionGenerator> generators;
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std::vector<InstructionGenerator> invalid;
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// List of instructions not to test
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const std::vector<std::string> do_not_test{
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// Dynarmic and QEMU currently differ on how the exclusive monitor's address range works.
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"STXR",
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"STLXR",
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"STXP",
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"STLXP",
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"LDXR",
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"LDAXR",
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"LDXP",
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"LDAXP",
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// Behaviour differs from QEMU
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"MSR_reg",
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"MSR_imm",
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"MRS",
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};
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for (const auto& [fn, bitstring] : list) {
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if (fn == "UnallocatedEncoding") {
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continue;
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}
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if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
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invalid.emplace_back(InstructionGenerator{bitstring});
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continue;
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}
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generators.emplace_back(InstructionGenerator{bitstring});
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}
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return InstructionGeneratorInfo{generators, invalid};
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}();
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while (true) {
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const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1);
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const u32 inst = instructions.generators[index].Generate();
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if (std::any_of(instructions.invalid.begin(), instructions.invalid.end(), [inst](const auto& invalid) { return invalid.Match(inst); })) {
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continue;
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}
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if (ShouldTestA64Inst(inst, pc, is_last_inst)) {
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return inst;
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}
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}
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}
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template<typename TestEnv>
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Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) {
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Dynarmic::A32::UserConfig GetA32UserConfig(TestEnv& testenv) {
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Dynarmic::A32::UserConfig user_config;
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user_config.optimizations &= ~OptimizationFlag::FastDispatch;
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user_config.callbacks = &testenv;
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@ -262,7 +346,7 @@ Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) {
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}
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template<size_t num_jit_reruns = 1, typename TestEnv>
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static void RunTestInstance(Dynarmic::A32::Jit& jit,
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void RunTestInstance(Dynarmic::A32::Jit& jit,
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TestEnv& jit_env,
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const std::array<u32, 16>& regs,
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const std::array<u32, 64>& vecs,
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@ -343,11 +427,104 @@ static void RunTestInstance(Dynarmic::A32::Jit& jit,
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fmt::print("===\n");
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}
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Dynarmic::A64::UserConfig GetA64UserConfig(A64TestEnv& jit_env) {
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Dynarmic::A64::UserConfig jit_user_config{&jit_env};
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jit_user_config.optimizations &= ~OptimizationFlag::FastDispatch;
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// The below corresponds to the settings for qemu's aarch64_max_initfn
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jit_user_config.dczid_el0 = 7;
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jit_user_config.ctr_el0 = 0x80038003;
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return jit_user_config;
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}
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template<size_t num_jit_reruns = 1>
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void RunTestInstance(Dynarmic::A64::Jit& jit,
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A64TestEnv& jit_env,
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const std::array<u64, 31>& regs,
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const std::array<std::array<u64, 2>, 32>& vecs,
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const std::vector<u32>& instructions,
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const u32 pstate,
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const u32 fpcr,
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const u64 initial_sp,
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const u64 start_address,
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const size_t ticks_left) {
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jit.ClearCache();
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for (size_t jit_rerun_count = 0; jit_rerun_count < num_jit_reruns; ++jit_rerun_count) {
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jit_env.code_mem = instructions;
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jit_env.code_mem.emplace_back(0x14000000); // B .
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jit_env.code_mem_start_address = start_address;
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jit_env.modified_memory.clear();
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jit_env.interrupts.clear();
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jit.SetRegisters(regs);
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jit.SetVectors(vecs);
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jit.SetPC(start_address);
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jit.SetSP(initial_sp);
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jit.SetFpcr(fpcr);
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jit.SetFpsr(0);
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jit.SetPstate(pstate);
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jit.ClearCache();
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jit_env.ticks_left = ticks_left;
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jit.Run();
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}
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fmt::print("instructions:");
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for (u32 instruction : instructions) {
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fmt::print(" {:08x}", instruction);
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}
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fmt::print("\n");
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fmt::print("initial_regs:");
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for (u64 i : regs) {
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fmt::print(" {:016x}", i);
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}
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fmt::print("\n");
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fmt::print("initial_vecs:");
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for (auto i : vecs) {
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fmt::print(" {:016x}:{:016x}", i[0], i[1]);
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}
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fmt::print("\n");
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fmt::print("initial_sp: {:016x}\n", initial_sp);
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fmt::print("initial_pstate: {:08x}\n", pstate);
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fmt::print("initial_fpcr: {:08x}\n", fpcr);
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fmt::print("final_regs:");
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for (u64 i : jit.GetRegisters()) {
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fmt::print(" {:016x}", i);
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}
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fmt::print("\n");
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fmt::print("final_vecs:");
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for (auto i : jit.GetVectors()) {
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fmt::print(" {:016x}:{:016x}", i[0], i[1]);
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}
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fmt::print("\n");
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fmt::print("final_sp: {:016x}\n", jit.GetSP());
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fmt::print("final_pc: {:016x}\n", jit.GetPC());
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fmt::print("final_pstate: {:08x}\n", jit.GetPstate());
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fmt::print("final_fpcr: {:08x}\n", jit.GetFpcr());
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fmt::print("final_qc : {}\n", FP::FPSR{jit.GetFpsr()}.QC());
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fmt::print("mod_mem:");
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for (auto [addr, value] : jit_env.modified_memory) {
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fmt::print(" {:08x}:{:02x}", addr, value);
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}
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fmt::print("\n");
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fmt::print("interrupts:\n");
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for (const auto& i : jit_env.interrupts) {
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std::puts(i.c_str());
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}
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fmt::print("===\n");
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}
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} // Anonymous namespace
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void TestThumb(size_t num_instructions, size_t num_iterations) {
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ThumbTestEnv jit_env{};
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Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
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Dynarmic::A32::Jit jit{GetA32UserConfig(jit_env)};
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std::array<u32, 16> regs;
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std::array<u32, 64> ext_reg;
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@ -374,7 +551,7 @@ void TestThumb(size_t num_instructions, size_t num_iterations) {
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void TestArm(size_t num_instructions, size_t num_iterations) {
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ArmTestEnv jit_env{};
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Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
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Dynarmic::A32::Jit jit{GetA32UserConfig(jit_env)};
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std::array<u32, 16> regs;
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std::array<u32, 64> ext_reg;
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@ -394,13 +571,43 @@ void TestArm(size_t num_instructions, size_t num_iterations) {
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}
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regs[15] = start_address;
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RunTestInstance(jit, jit_env, regs, ext_reg, instructions, cpsr, fpcr, 1);
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RunTestInstance(jit, jit_env, regs, ext_reg, instructions, cpsr, fpcr, num_instructions);
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}
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}
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void TestA64(size_t num_instructions, size_t num_iterations) {
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A64TestEnv jit_env{};
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Dynarmic::A64::Jit jit{GetA64UserConfig(jit_env)};
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std::array<u64, 31> regs;
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std::array<std::array<u64, 2>, 32> vecs;
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std::vector<u32> instructions;
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for (size_t iteration = 0; iteration < num_iterations; ++iteration) {
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std::generate(regs.begin(), regs.end(), [] { return RandInt<u64>(0, ~u64(0)); });
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std::generate(vecs.begin(), vecs.end(), RandomVector);
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const u32 start_address = 100;
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const u32 pstate = (RandInt<u32>(0, 0xF) << 28);
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const u32 fpcr = RandomFpcr();
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const u64 initial_sp = RandInt<u64>(0x30'0000'0000, 0x40'0000'0000) * 4;
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instructions.clear();
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for (size_t i = 0; i < num_instructions; ++i) {
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instructions.emplace_back(GenRandomA64Inst(static_cast<u32>(start_address + 4 * instructions.size()), i == num_instructions - 1));
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}
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RunTestInstance(jit, jit_env, regs, vecs, instructions, pstate, fpcr, initial_sp, start_address, num_instructions);
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}
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}
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int main(int, char*[]) {
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detail::g_rand_int_generator.seed(42069);
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TestThumb(1, 1);
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TestArm(1, 1);
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TestA64(1, 1);
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TestThumb(1, 100000);
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TestArm(1, 100000);
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TestThumb(5, 100000);
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