A32: Implement ARM-mode UBFX

src/frontend/A32/decoder/arm.inc

@@ -169,6 +169,7 @@ INST(arm_BFI,           "BFI",                 "cccc0111110vvvvvddddvvvvv001nnnn
 INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
 INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6
+INST(arm_UBFX,          "UBFX",                "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
 
 // Unsigned Sum of Absolute Differences instructions
 INST(arm_USAD8,         "USAD8",               "cccc01111000dddd1111mmmm0001nnnn") // v6

src/frontend/A32/disassembler/disassembler_arm.cpp

@@ -601,6 +601,9 @@ public:
     std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
         return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m);
     }
+    std::string arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+        return fmt::format("ubfx{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, widthm1 + 1);
+    }
 
     // Unsigned sum of absolute difference functions
     std::string arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {

src/frontend/A32/translate/translate_arm/misc.cpp

@@ -85,4 +85,27 @@ bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
     return true;
 }
 
+// UBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
+bool ArmTranslatorVisitor::arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
+    if (d == Reg::PC || n == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const u32 msb = u32{lsb} + widthm1;
+    if (msb >= Common::BitSize<u32>()) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 operand = ir.GetRegister(n);
+    const IR::U32 mask = ir.Imm32(Common::Ones<u32>(widthm1 + 1));
+    const IR::U32 result = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(lsb)), mask);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 } // namespace Dynarmic::A32

src/frontend/A32/translate/translate_arm/translate_arm.h

@@ -213,6 +213,7 @@ struct ArmTranslatorVisitor final {
     bool arm_NOP() { return true; }
     bool arm_RBIT(Cond cond, Reg d, Reg m);
     bool arm_SEL(Cond cond, Reg n, Reg d, Reg m);
+    bool arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n);
 
     // Unsigned sum of absolute difference functions
     bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n);

tests/A32/fuzz_arm.cpp

@@ -1093,11 +1093,22 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
         // R15 as Rd, or Rm is UNPREDICTABLE
         return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111;
     };
+    const auto is_ubfx_valid = [](u32 instr) {
+        const u32 lsb = Bits<7, 11>(instr);
+        const u32 widthm1 = Bits<16, 20>(instr);
+        const u32 msb = lsb + widthm1;
+
+        // Rd or Rn as R15 or the case where msb > 32 is UNPREDICTABLE.
+        return Bits<0, 3>(instr) != 0b1111 &&
+               Bits<12, 15>(instr) != 0b1111 &&
+               msb < Dynarmic::Common::BitSize<u32>();
+    };
 
     const std::array instructions = {
         InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC
         InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI
         InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid),     // CLZ
+        InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_ubfx_valid),    // UBFX
     };
 
     FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {