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A64: Move SDIV and UDIV out of data_processing_multiply.cpp

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Lioncash 2018-02-06 19:29:53 -05:00 committed by MerryMage
parent 35a29a9665
commit 4e33629b0e
2 changed files with 24 additions and 24 deletions
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24
src/frontend/A64/translate/impl/data_processing_multiply.cpp
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@ -98,28 +98,4 @@ bool TranslatorVisitor::UMULH(Reg Rm, Reg Rn, Reg Rd) {
return true; return true;
} }
bool TranslatorVisitor::UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 m = X(datasize, Rm);
const IR::U32U64 n = X(datasize, Rn);
const IR::U32U64 result = ir.UnsignedDiv(n,m);
X(datasize, Rd, result);
return true;
}
bool TranslatorVisitor::SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 m = X(datasize, Rm);
const IR::U32U64 n = X(datasize, Rn);
const IR::U32U64 result = ir.SignedDiv(n,m);
X(datasize, Rd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64

24
src/frontend/A64/translate/impl/data_processing_register.cpp
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@ -112,4 +112,28 @@ bool TranslatorVisitor::REV16_int(bool sf, Reg Rn, Reg Rd) {
return true; return true;
} }
bool TranslatorVisitor::UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 m = X(datasize, Rm);
const IR::U32U64 n = X(datasize, Rn);
const IR::U32U64 result = ir.UnsignedDiv(n,m);
X(datasize, Rd, result);
return true;
}
bool TranslatorVisitor::SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
const IR::U32U64 m = X(datasize, Rm);
const IR::U32U64 n = X(datasize, Rn);
const IR::U32U64 result = ir.SignedDiv(n,m);
X(datasize, Rd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64