IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub}
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MerryMage
parent
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commit
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5 changed files with 471 additions and 0 deletions
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@ -257,6 +257,7 @@ if (ARCHITECTURE_x86_64)
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backend/x64/emit_x64_sm4.cpp
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backend/x64/emit_x64_vector.cpp
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backend/x64/emit_x64_vector_floating_point.cpp
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backend/x64/emit_x64_vector_saturation.cpp
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backend/x64/exception_handler.h
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backend/x64/hostloc.cpp
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backend/x64/hostloc.h
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370
src/backend/x64/emit_x64_vector_saturation.cpp
Normal file
370
src/backend/x64/emit_x64_vector_saturation.cpp
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@ -0,0 +1,370 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "backend/x64/block_of_code.h"
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#include "backend/x64/emit_x64.h"
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#include "common/common_types.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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namespace Dynarmic::Backend::X64 {
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using namespace Xbyak::util;
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namespace {
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void EmitVectorSaturatedNative(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, void (Xbyak::CodeGenerator::*saturated_fn)(const Xbyak::Mmx& mmx, const Xbyak::Operand&), void (Xbyak::CodeGenerator::*unsaturated_fn)(const Xbyak::Mmx& mmx, const Xbyak::Operand&), void (Xbyak::CodeGenerator::*sub_fn)(const Xbyak::Mmx& mmx, const Xbyak::Operand&)) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm addend = ctx.reg_alloc.UseXmm(args[1]);
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if (overflow_inst) {
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code.movaps(xmm0, result);
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}
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(code.*saturated_fn)(result, addend);
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if (overflow_inst) {
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const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr().cvt8();
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(code.*unsaturated_fn)(xmm0, addend);
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(code.*sub_fn)(xmm0, result);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.ptest(xmm0, xmm0);
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} else {
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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code.pxor(tmp, tmp);
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code.pcmpeqw(xmm0, tmp);
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code.pmovmskb(overflow.cvt32(), xmm0);
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code.xor_(overflow.cvt32(), 0xFFFF);
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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enum class Op {
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Add,
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Sub,
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};
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template<Op op, size_t esize>
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void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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static_assert(esize == 32 || esize == 64);
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constexpr u64 msb_mask = esize == 32 ? 0x8000000080000000 : 0x8000000000000000;
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm arg = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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// TODO AVX-512: vpternlog, vpsraq
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// TODO AVX2 implementation
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code.movaps(xmm0, result);
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code.movaps(tmp, result);
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if constexpr (op == Op::Add) {
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if constexpr (esize == 32) {
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code.paddd(result, arg);
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} else {
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code.paddq(result, arg);
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}
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} else {
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if constexpr (esize == 32) {
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code.psubd(result, arg);
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} else {
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code.psubq(result, arg);
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}
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}
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code.pxor(tmp, result);
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code.pxor(xmm0, arg);
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if constexpr (op == Op::Add) {
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code.pandn(xmm0, tmp);
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} else {
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code.pand(xmm0, tmp);
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}
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code.movaps(tmp, result);
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code.psrad(tmp, 31);
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if constexpr (esize == 64) {
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code.pshufd(tmp, tmp, 0b11110101);
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}
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code.pxor(tmp, code.MConst(xword, msb_mask, msb_mask));
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if (overflow_inst) {
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const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr().cvt8();
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.ptest(xmm0, code.MConst(xword, msb_mask, msb_mask));
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} else {
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if constexpr (esize == 32) {
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code.movmskps(overflow.cvt32(), xmm0);
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} else {
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code.movmskpd(overflow.cvt32(), xmm0);
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}
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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if constexpr (esize == 32) {
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code.blendvps(result, tmp);
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} else {
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code.blendvpd(result, tmp);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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code.psrad(xmm0, 31);
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if constexpr (esize == 64) {
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code.pshufd(xmm0, xmm0, 0b11110101);
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}
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code.pand(tmp, xmm0);
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code.pandn(xmm0, result);
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code.por(tmp, xmm0);
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ctx.reg_alloc.DefineValue(inst, tmp);
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}
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}
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} // anonymous namespace
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void EmitX64::EmitVectorSignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::paddsb, &Xbyak::CodeGenerator::paddb, &Xbyak::CodeGenerator::psubb);
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}
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void EmitX64::EmitVectorSignedSaturatedAdd16(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::paddsw, &Xbyak::CodeGenerator::paddw, &Xbyak::CodeGenerator::psubw);
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}
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void EmitX64::EmitVectorSignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturated<Op::Add, 32>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturated<Op::Add, 64>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedSub8(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::psubsb, &Xbyak::CodeGenerator::psubb, &Xbyak::CodeGenerator::psubb);
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}
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void EmitX64::EmitVectorSignedSaturatedSub16(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::psubsw, &Xbyak::CodeGenerator::psubw, &Xbyak::CodeGenerator::psubw);
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}
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void EmitX64::EmitVectorSignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturated<Op::Sub, 32>(code, ctx, inst);
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}
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void EmitX64::EmitVectorSignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSignedSaturated<Op::Sub, 64>(code, ctx, inst);
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}
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void EmitX64::EmitVectorUnsignedSaturatedAdd8(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::paddusb, &Xbyak::CodeGenerator::paddb, &Xbyak::CodeGenerator::psubb);
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}
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void EmitX64::EmitVectorUnsignedSaturatedAdd16(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::paddusw, &Xbyak::CodeGenerator::paddw, &Xbyak::CodeGenerator::psubw);
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}
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void EmitX64::EmitVectorUnsignedSaturatedAdd32(EmitContext& ctx, IR::Inst* inst) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm addend = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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// TODO AVX2, AVX-512: vpternlog
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code.movaps(tmp, result);
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code.movaps(xmm0, result);
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code.pxor(xmm0, addend);
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code.pand(tmp, addend);
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code.paddd(result, addend);
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code.psrld(xmm0, 1);
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code.paddd(tmp, xmm0);
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code.psrad(tmp, 31);
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code.por(result, tmp);
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if (overflow_inst) {
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const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr().cvt8();
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.ptest(tmp, tmp);
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} else {
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code.movmskps(overflow.cvt32(), tmp);
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitVectorUnsignedSaturatedAdd64(EmitContext& ctx, IR::Inst* inst) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm addend = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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// TODO AVX2, AVX-512: vpternlog
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code.movaps(tmp, result);
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code.movaps(xmm0, result);
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code.pxor(xmm0, addend);
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code.pand(tmp, addend);
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code.paddq(result, addend);
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code.psrlq(xmm0, 1);
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code.paddq(tmp, xmm0);
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code.psrad(tmp, 31);
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code.pshufd(tmp, tmp, 0b11110101);
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code.por(result, tmp);
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if (overflow_inst) {
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const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr().cvt8();
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.ptest(tmp, tmp);
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} else {
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code.movmskpd(overflow.cvt32(), tmp);
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitVectorUnsignedSaturatedSub8(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::psubusb, &Xbyak::CodeGenerator::psubb, &Xbyak::CodeGenerator::psubb);
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}
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void EmitX64::EmitVectorUnsignedSaturatedSub16(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorSaturatedNative(code, ctx, inst, &Xbyak::CodeGenerator::psubusw, &Xbyak::CodeGenerator::psubw, &Xbyak::CodeGenerator::psubw);
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}
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void EmitX64::EmitVectorUnsignedSaturatedSub32(EmitContext& ctx, IR::Inst* inst) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm subtrahend = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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// TODO AVX2, AVX-512: vpternlog
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code.movaps(tmp, result);
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code.movaps(xmm0, subtrahend);
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code.pxor(tmp, subtrahend);
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code.psubd(result, subtrahend);
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code.pand(xmm0, tmp);
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code.psrld(tmp, 1);
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code.psubd(tmp, xmm0);
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code.psrad(tmp, 31);
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if (overflow_inst) {
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const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr().cvt8();
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.ptest(tmp, tmp);
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} else {
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code.movmskps(overflow.cvt32(), tmp);
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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code.pandn(tmp, result);
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ctx.reg_alloc.DefineValue(inst, tmp);
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}
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void EmitX64::EmitVectorUnsignedSaturatedSub64(EmitContext& ctx, IR::Inst* inst) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm subtrahend = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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// TODO AVX2, AVX-512: vpternlog
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code.movaps(tmp, result);
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code.movaps(xmm0, subtrahend);
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code.pxor(tmp, subtrahend);
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code.psubq(result, subtrahend);
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code.pand(xmm0, tmp);
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code.psrlq(tmp, 1);
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code.psubq(tmp, xmm0);
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code.psrad(tmp, 31);
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code.pshufd(tmp, tmp, 0b11110101);
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if (overflow_inst) {
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const Xbyak::Reg8 overflow = ctx.reg_alloc.ScratchGpr().cvt8();
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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code.ptest(tmp, tmp);
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} else {
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code.movmskpd(overflow.cvt32(), tmp);
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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code.pandn(tmp, result);
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ctx.reg_alloc.DefineValue(inst, tmp);
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}
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} // namespace Dynarmic::Backend::X64
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@ -635,6 +635,83 @@ ResultAndOverflow<U32> IREmitter::UnsignedSaturation(const U32& a, size_t bit_si
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return {result, overflow};
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}
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ResultAndOverflow<U128> IREmitter::VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
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const auto result = [&]{
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switch (esize) {
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case 8:
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return Inst<U128>(Opcode::VectorSignedSaturatedAdd8, a, b);
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case 16:
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return Inst<U128>(Opcode::VectorSignedSaturatedAdd16, a, b);
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case 32:
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return Inst<U128>(Opcode::VectorSignedSaturatedAdd32, a, b);
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case 64:
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return Inst<U128>(Opcode::VectorSignedSaturatedAdd64, a, b);
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default:
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UNREACHABLE();
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}
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}();
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const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
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return {result, overflow};
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}
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ResultAndOverflow<U128> IREmitter::VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
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const auto result = [&]{
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switch (esize) {
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case 8:
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return Inst<U128>(Opcode::VectorSignedSaturatedSub8, a, b);
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case 16:
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return Inst<U128>(Opcode::VectorSignedSaturatedSub16, a, b);
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case 32:
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return Inst<U128>(Opcode::VectorSignedSaturatedSub32, a, b);
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case 64:
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return Inst<U128>(Opcode::VectorSignedSaturatedSub64, a, b);
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default:
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UNREACHABLE();
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}
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}();
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const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
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return {result, overflow};
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}
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ResultAndOverflow<U128> IREmitter::VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b) {
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const auto result = [&]{
|
||||
switch (esize) {
|
||||
case 8:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd8, a, b);
|
||||
case 16:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd16, a, b);
|
||||
case 32:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd32, a, b);
|
||||
case 64:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedAdd64, a, b);
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}();
|
||||
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
|
||||
return {result, overflow};
|
||||
}
|
||||
|
||||
ResultAndOverflow<U128> IREmitter::VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b) {
|
||||
const auto result = [&]{
|
||||
switch (esize) {
|
||||
case 8:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub8, a, b);
|
||||
case 16:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub16, a, b);
|
||||
case 32:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub32, a, b);
|
||||
case 64:
|
||||
return Inst<U128>(Opcode::VectorUnsignedSaturatedSub64, a, b);
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}();
|
||||
const auto overflow = Inst<U1>(Opcode::GetOverflowFromOp, result);
|
||||
return {result, overflow};
|
||||
}
|
||||
|
||||
|
||||
ResultAndGE<U32> IREmitter::PackedAddU8(const U32& a, const U32& b) {
|
||||
const auto result = Inst<U32>(Opcode::PackedAddU8, a, b);
|
||||
const auto ge = Inst<U32>(Opcode::GetGEFromOp, result);
|
||||
|
|
|
|||
|
|
@ -166,6 +166,11 @@ public:
|
|||
ResultAndOverflow<UAny> UnsignedSaturatedSub(const UAny& a, const UAny& b);
|
||||
ResultAndOverflow<U32> UnsignedSaturation(const U32& a, size_t bit_size_to_saturate_to);
|
||||
|
||||
ResultAndOverflow<U128> VectorSignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
|
||||
ResultAndOverflow<U128> VectorSignedSaturatedSub(size_t esize, const U128& a, const U128& b);
|
||||
ResultAndOverflow<U128> VectorUnsignedSaturatedAdd(size_t esize, const U128& a, const U128& b);
|
||||
ResultAndOverflow<U128> VectorUnsignedSaturatedSub(size_t esize, const U128& a, const U128& b);
|
||||
|
||||
ResultAndGE<U32> PackedAddU8(const U32& a, const U32& b);
|
||||
ResultAndGE<U32> PackedAddS8(const U32& a, const U32& b);
|
||||
ResultAndGE<U32> PackedAddU16(const U32& a, const U32& b);
|
||||
|
|
|
|||
|
|
@ -194,6 +194,24 @@ OPCODE(UnsignedSaturatedSub32, U32, U32,
|
|||
OPCODE(UnsignedSaturatedSub64, U64, U64, U64 )
|
||||
OPCODE(UnsignedSaturation, U32, U32, U8 )
|
||||
|
||||
// Vector saturated instructions
|
||||
OPCODE(VectorSignedSaturatedAdd8, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedAdd16, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedAdd32, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedAdd64, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedSub8, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedSub16, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedSub32, U128, U128, U128 )
|
||||
OPCODE(VectorSignedSaturatedSub64, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedAdd8, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedAdd16, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedAdd32, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedAdd64, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedSub8, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedSub16, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedSub32, U128, U128, U128 )
|
||||
OPCODE(VectorUnsignedSaturatedSub64, U128, U128, U128 )
|
||||
|
||||
// Packed instructions
|
||||
OPCODE(PackedAddU8, U32, U32, U32 )
|
||||
OPCODE(PackedAddS8, U32, U32, U32 )
|
||||
|
|
|
|||
Loading…
Reference in a new issue