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parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15

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MerryMage 2017-04-25 13:45:31 +01:00
parent 7639dfea51
commit 50bb317104
1 changed files with 4 additions and 0 deletions
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4
src/frontend/translate/translate_arm/parallel.cpp
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@ -205,6 +205,8 @@ bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedAddU8(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedAddU8(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);
@ -213,6 +215,8 @@ bool ArmTranslatorVisitor::arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) {
} }
bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
auto result = ir.PackedSaturatedAddU16(ir.GetRegister(n), ir.GetRegister(m)); auto result = ir.PackedSaturatedAddU16(ir.GetRegister(n), ir.GetRegister(m));
ir.SetRegister(d, result); ir.SetRegister(d, result);