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thumb32: Implement LDRSB variants

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This commit is contained in:
Lioncash 2021-03-06 11:14:33 -05:00
parent fe892732cf
commit 52fdf801d0
3 changed files with 103 additions and 43 deletions
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10
src/frontend/A32/decoder/thumb32.inc
View file

@ -158,11 +158,11 @@ INST(thumb32_LDRB_reg, "LDRB (reg)", "111110000001nnnntttt00
INST(thumb32_LDRBT, "LDRBT", "111110000001nnnntttt1110iiiiiiii")
INST(thumb32_LDRB_imm8, "LDRB (imm8)", "111110000001nnnntttt1PUWiiiiiiii")
INST(thumb32_LDRB_imm12, "LDRB (imm12)", "111110001001nnnnttttiiiiiiiiiiii")
//INST(thumb32_LDRSB_lit, "LDRSB (lit)", "11111001-0011111----------------")
//INST(thumb32_LDRSB_reg, "LDRSB (reg)", "111110010001--------000000------")
//INST(thumb32_LDRSBT, "LDRSBT", "111110010001--------1110--------")
//INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001--------1-----------")
//INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001--------------------")
INST(thumb32_LDRSB_lit, "LDRSB (lit)", "11111001U0011111ttttiiiiiiiiiiii")
INST(thumb32_LDRSB_reg, "LDRSB (reg)", "111110010001nnnntttt000000iimmmm")
INST(thumb32_LDRSBT, "LDRSBT", "111110010001nnnntttt1110iiiiiiii")
INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001nnnntttt1PUWiiiiiiii")
INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001nnnnttttiiiiiiiiiiii")
// Load Halfword and Memory Hints
//INST(thumb32_LDRH_lit, "LDRH (lit)", "11111000-0111111----------------")

131
src/frontend/A32/translate/impl/thumb32_load_byte.cpp
View file

@ -25,6 +25,51 @@ static bool PLIHandler(ThumbTranslatorVisitor& v) {
return v.RaiseException(Exception::PreloadInstruction);
}
using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U8&);
static bool LoadByteLiteral(ThumbTranslatorVisitor& v, bool U, Reg t, Imm<12> imm12,
ExtensionFunction ext_fn) {
const u32 imm32 = imm12.ZeroExtend();
const u32 base = v.ir.AlignPC(4);
const u32 address = U ? (base + imm32) : (base - imm32);
const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory8(v.ir.Imm32(address)));
v.ir.SetRegister(t, data);
return true;
}
static bool LoadByteRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m,
ExtensionFunction ext_fn) {
if (m == Reg::PC) {
return v.UnpredictableInstruction();
}
const auto reg_n = v.ir.GetRegister(n);
const auto reg_m = v.ir.GetRegister(m);
const auto offset = v.ir.LogicalShiftLeft(reg_m, v.ir.Imm8(imm2.ZeroExtend<u8>()));
const auto address = v.ir.Add(reg_n, offset);
const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory8(address));
v.ir.SetRegister(t, data);
return true;
}
static bool LoadByteImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W,
Imm<12> imm12, ExtensionFunction ext_fn) {
const u32 imm32 = imm12.ZeroExtend();
const IR::U32 reg_n = v.ir.GetRegister(n);
const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32))
: v.ir.Sub(reg_n, v.ir.Imm32(imm32));
const IR::U32 address = P ? offset_address : reg_n;
const IR::U32 data = (v.ir.*ext_fn)(v.ir.ReadMemory8(address));
v.ir.SetRegister(t, data);
if (W) {
v.ir.SetRegister(n, offset_address);
}
return true;
}
bool ThumbTranslatorVisitor::thumb32_PLD_lit([[maybe_unused]] bool U,
[[maybe_unused]] Imm<12> imm12) {
return PLDHandler(*this, false);
@ -79,13 +124,7 @@ bool ThumbTranslatorVisitor::thumb32_PLI_reg([[maybe_unused]] Reg n,
}
bool ThumbTranslatorVisitor::thumb32_LDRB_lit(bool U, Reg t, Imm<12> imm12) {
const u32 imm32 = imm12.ZeroExtend();
const u32 base = ir.AlignPC(4);
const u32 address = U ? (base + imm32) : (base - imm32);
const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(ir.Imm32(address)));
ir.SetRegister(t, data);
return true;
return LoadByteLiteral(*this, U, t, imm12, &IREmitter::ZeroExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
@ -99,43 +138,17 @@ bool ThumbTranslatorVisitor::thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, boo
return UndefinedInstruction();
}
const u32 imm32 = imm8.ZeroExtend();
const IR::U32 reg_n = ir.GetRegister(n);
const IR::U32 offset_address = U ? ir.Add(reg_n, ir.Imm32(imm32))
: ir.Sub(reg_n, ir.Imm32(imm32));
const IR::U32 address = P ? offset_address : reg_n;
const IR::U32 data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
ir.SetRegister(t, data);
if (W) {
ir.SetRegister(n, offset_address);
}
return true;
return LoadByteImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
&IREmitter::ZeroExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12) {
const auto imm32 = imm12.ZeroExtend();
const auto reg_n = ir.GetRegister(n);
const auto address = ir.Add(reg_n, ir.Imm32(imm32));
const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
ir.SetRegister(t, data);
return true;
return LoadByteImmediate(*this, n, t, true, true, false, imm12,
&IREmitter::ZeroExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
if (m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_n = ir.GetRegister(n);
const auto reg_m = ir.GetRegister(m);
const auto offset = ir.LogicalShiftLeft(reg_m, ir.Imm8(imm2.ZeroExtend<u8>()));
const auto address = ir.Add(reg_n, offset);
const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
ir.SetRegister(t, data);
return true;
return LoadByteRegister(*this, n, t, imm2, m, &IREmitter::ZeroExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8) {
@ -152,4 +165,46 @@ bool ThumbTranslatorVisitor::thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8) {
return thumb32_LDRB_imm8(n, t, true, true, false, imm8);
}
bool ThumbTranslatorVisitor::thumb32_LDRSB_lit(bool U, Reg t, Imm<12> imm12) {
return LoadByteLiteral(*this, U, t, imm12, &IREmitter::SignExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRSB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
if (t == Reg::PC && W) {
return UnpredictableInstruction();
}
if (W && n == t) {
return UnpredictableInstruction();
}
if (!P && !W) {
return UndefinedInstruction();
}
return LoadByteImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
&IREmitter::SignExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12) {
return LoadByteImmediate(*this, n, t, true, true, false, imm12,
&IREmitter::SignExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRSB_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
return LoadByteRegister(*this, n, t, imm2, m, &IREmitter::SignExtendByteToWord);
}
bool ThumbTranslatorVisitor::thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8) {
// TODO: Add an unpredictable instruction path if this
// is executed in hypervisor mode if we ever support
// privileged execution modes.
if (t == Reg::PC) {
return UnpredictableInstruction();
}
// Treat it as a normal LDRSB, given we don't support
// execution levels other than EL0 currently.
return thumb32_LDRSB_imm8(n, t, true, true, false, imm8);
}
} // namespace Dynarmic::A32

5
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -219,6 +219,11 @@ struct ThumbTranslatorVisitor final {
bool thumb32_LDRB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
bool thumb32_LDRB_imm12(Reg n, Reg t, Imm<12> imm12);
bool thumb32_LDRBT(Reg n, Reg t, Imm<8> imm8);
bool thumb32_LDRSB_lit(bool U, Reg t, Imm<12> imm12);
bool thumb32_LDRSB_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
bool thumb32_LDRSB_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
bool thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12);
bool thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8);
// thumb32 data processing (register) instructions
bool thumb32_ASR_reg(Reg m, Reg d, Reg s);