thumb32: Implement SMMLS{R}

This commit is contained in:
Lioncash 2021-02-07 13:23:19 -05:00
parent 0c542777b0
commit 53f1a52be9
3 changed files with 21 additions and 1 deletions

View file

@ -274,7 +274,7 @@ INST(thumb32_SMUSD, "SMUSD", "111110110100nnnn1111dd
//INST(thumb32_SMLSD, "SMLSD", "111110110100------------000-----")
INST(thumb32_SMMUL, "SMMUL", "111110110101nnnn1111dddd000Rmmmm")
INST(thumb32_SMMLA, "SMMLA", "111110110101nnnnaaaadddd000Rmmmm")
//INST(thumb32_SMMLS, "SMMLS", "111110110110------------000-----")
INST(thumb32_SMMLS, "SMMLS", "111110110110nnnnaaaadddd000Rmmmm")
INST(thumb32_USAD8, "USAD8", "111110110111nnnn1111dddd0000mmmm")
INST(thumb32_USADA8, "USADA8", "111110110111nnnnaaaadddd0000mmmm")

View file

@ -86,6 +86,25 @@ bool ThumbTranslatorVisitor::thumb32_SMMLA(Reg n, Reg a, Reg d, bool R, Reg m) {
return true;
}
bool ThumbTranslatorVisitor::thumb32_SMMLS(Reg n, Reg a, Reg d, bool R, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC) {
return UnpredictableInstruction();
}
const auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
const auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
const auto a64 = ir.Pack2x32To1x64(ir.Imm32(0), ir.GetRegister(a));
const auto temp = ir.Sub(a64, ir.Mul(n64, m64));
const auto result_carry = ir.MostSignificantWord(temp);
auto result = result_carry.result;
if (R) {
result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
}
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_SMMUL(Reg n, Reg d, bool R, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();

View file

@ -134,6 +134,7 @@ struct ThumbTranslatorVisitor final {
bool thumb32_MUL(Reg n, Reg d, Reg m);
bool thumb32_SMLAXY(Reg n, Reg a, Reg d, bool N, bool M, Reg m);
bool thumb32_SMMLA(Reg n, Reg a, Reg d, bool R, Reg m);
bool thumb32_SMMLS(Reg n, Reg a, Reg d, bool R, Reg m);
bool thumb32_SMMUL(Reg n, Reg d, bool R, Reg m);
bool thumb32_SMUAD(Reg n, Reg d, bool M, Reg m);
bool thumb32_SMUSD(Reg n, Reg d, bool M, Reg m);