backend/x64: Touch PEXT/PDEP code
* Use pext/pdep where not previously used * Limit pext/pdep to non-AMD platforms due to slowness on AMD * Use imul/and as alternatives for AMD and non-BMI2 platforms
This commit is contained in:
MerryMage
parent
f495018f53
commit
55bddc767f
5 changed files with 125 additions and 62 deletions
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@ -412,16 +412,12 @@ void A32EmitX64::EmitA32SetVector(A32EmitContext& ctx, IR::Inst* inst) {
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}
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}
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static u32 GetCpsrImpl(A32JitState* jit_state) {
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return jit_state->Cpsr();
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}
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void A32EmitX64::EmitA32GetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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if (code.HasBMI2()) {
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const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp2 = ctx.reg_alloc.ScratchGpr().cvt32();
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if (code.HasFastBMI2()) {
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// Here we observe that cpsr_et and cpsr_ge are right next to each other in memory,
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// so we load them both at the same time with one 64-bit read. This allows us to
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// extract all of their bits together at once with one pext.
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@ -431,32 +427,43 @@ void A32EmitX64::EmitA32GetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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code.pext(result.cvt64(), result.cvt64(), tmp.cvt64());
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code.mov(tmp, 0x000f0220);
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code.pdep(result, result, tmp);
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} else {
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code.mov(result, dword[r15 + offsetof(A32JitState, upper_location_descriptor)]);
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code.imul(result, result, 0x12);
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code.and_(result, 0x00000220);
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code.mov(tmp, dword[r15 + offsetof(A32JitState, cpsr_ge)]);
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code.and_(tmp, 0x80808080);
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code.imul(tmp, tmp, 0x00204081);
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code.shr(tmp, 12);
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code.and_(tmp, 0x000f0000);
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code.or_(result, tmp);
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}
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code.mov(tmp, dword[r15 + offsetof(A32JitState, cpsr_q)]);
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code.shl(tmp, 27);
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code.or_(result, tmp);
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code.mov(tmp2, dword[r15 + offsetof(A32JitState, cpsr_nzcv)]);
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if (code.HasFastBMI2()) {
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code.mov(tmp, NZCV::x64_mask);
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code.pext(tmp2, tmp2, tmp);
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code.shl(tmp2, 28);
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} else {
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code.and_(tmp2, NZCV::x64_mask);
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code.imul(tmp2, tmp2, NZCV::from_x64_multiplier);
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code.and_(tmp2, NZCV::arm_mask);
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}
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code.or_(result, tmp2);
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code.or_(result, dword[r15 + offsetof(A32JitState, cpsr_jaifm)]);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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ctx.reg_alloc.HostCall(inst);
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code.mov(code.ABI_PARAM1, code.r15);
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code.CallFunction(&GetCpsrImpl);
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}
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}
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static void SetCpsrImpl(u32 value, A32JitState* jit_state) {
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jit_state->SetCpsr(value);
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}
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void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.HasBMI2()) {
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const Xbyak::Reg32 cpsr = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 tmp2 = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -472,8 +479,13 @@ void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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// cpsr_nzcv
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code.mov(tmp, cpsr);
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code.shr(tmp, 28);
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if (code.HasFastBMI2()) {
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code.mov(tmp2, NZCV::x64_mask);
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code.pdep(tmp, tmp, tmp2);
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} else {
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code.imul(tmp, tmp, NZCV::to_x64_multiplier);
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code.and_(tmp, NZCV::x64_mask);
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}
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_nzcv)], tmp);
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// cpsr_jaifm
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@ -481,10 +493,12 @@ void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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code.and_(tmp, 0x07F0FDDF);
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_jaifm)], tmp);
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if (code.HasFastBMI2()) {
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// cpsr_et and cpsr_ge
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static_assert(offsetof(A32JitState, upper_location_descriptor) + 4 == offsetof(A32JitState, cpsr_ge));
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// This mask is 0x7FFF0000, because we do not want the MSB to be sign extended to the upper dword.
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static_assert((A32::LocationDescriptor::FPSCR_MODE_MASK & ~0x7FFF0000) == 0);
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code.and_(qword[r15 + offsetof(A32JitState, upper_location_descriptor)], u32(0x7FFF0000));
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code.mov(tmp, 0x000f0220);
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code.pext(cpsr, cpsr, tmp);
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@ -497,14 +511,21 @@ void A32EmitX64::EmitA32SetCpsr(A32EmitContext& ctx, IR::Inst* inst) {
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code.xor_(tmp.cvt64(), tmp2.cvt64());
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code.or_(qword[r15 + offsetof(A32JitState, upper_location_descriptor)], tmp.cvt64());
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} else {
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ctx.reg_alloc.HostCall(nullptr, args[0]);
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code.and_(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], u32(0xFFFF0000));
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code.mov(tmp, cpsr);
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code.and_(tmp, 0x00000220);
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code.imul(tmp, tmp, 0x00900000);
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code.shr(tmp, 28);
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code.or_(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], tmp);
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if (config.always_little_endian) {
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code.and_(code.ABI_PARAM1, 0xFFFFFDFF);
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}
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code.mov(code.ABI_PARAM2, code.r15);
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code.CallFunction(&SetCpsrImpl);
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code.and_(cpsr, 0x000f0000);
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code.shr(cpsr, 16);
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code.imul(cpsr, cpsr, 0x00204081);
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code.and_(cpsr, 0x01010101);
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code.mov(tmp, 0x80808080);
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code.sub(tmp, cpsr);
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code.xor_(tmp, 0x80808080);
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_ge)], tmp);
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}
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}
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@ -514,7 +535,7 @@ void A32EmitX64::EmitA32SetCpsrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
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const u32 imm = args[0].GetImmediateU32();
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_nzcv)], NZCV::ToX64(imm));
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} else if (code.HasBMI2()) {
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} else if (code.HasFastBMI2()) {
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const Xbyak::Reg32 a = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 b = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -539,7 +560,7 @@ void A32EmitX64::EmitA32SetCpsrNZCVQ(A32EmitContext& ctx, IR::Inst* inst) {
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_nzcv)], NZCV::ToX64(imm));
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code.mov(code.byte[r15 + offsetof(A32JitState, cpsr_q)], u8((imm & 0x08000000) != 0 ? 1 : 0));
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} else if (code.HasBMI2()) {
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} else if (code.HasFastBMI2()) {
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const Xbyak::Reg32 a = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 b = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -666,7 +687,7 @@ void A32EmitX64::EmitA32SetGEFlagsCompressed(A32EmitContext& ctx, IR::Inst* inst
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ge |= Common::Bit<16>(imm) ? 0x000000FF : 0;
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code.mov(dword[r15 + offsetof(A32JitState, cpsr_ge)], ge);
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} else if (code.HasBMI2()) {
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} else if (code.HasFastBMI2()) {
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const Xbyak::Reg32 a = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 b = ctx.reg_alloc.ScratchGpr().cvt32();
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@ -802,13 +823,24 @@ void A32EmitX64::EmitA32GetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
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void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (code.HasFastBMI2()) {
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const Xbyak::Reg32 value = ctx.reg_alloc.UseGpr(args[0]).cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(tmp, NZCV::x64_mask);
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code.pext(tmp, value, tmp);
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code.shl(tmp, 28);
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code.mov(dword[r15 + offsetof(A32JitState, fpsr_nzcv)], tmp);
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return;
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}
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const Xbyak::Reg32 value = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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code.and_(value, 0b11000001'00000001);
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code.imul(value, value, 0b00010000'00100001);
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code.shl(value, 16);
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code.and_(value, 0xF0000000);
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code.and_(value, NZCV::x64_mask);
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code.imul(value, value, NZCV::from_x64_multiplier);
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code.and_(value, NZCV::arm_mask);
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code.mov(dword[r15 + offsetof(A32JitState, fpsr_nzcv)], value);
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}
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@ -381,9 +381,18 @@ void A64EmitX64::EmitA64GetNZCVRaw(A64EmitContext& ctx, IR::Inst* inst) {
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const Xbyak::Reg32 nzcv_raw = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(nzcv_raw, dword[r15 + offsetof(A64JitState, cpsr_nzcv)]);
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if (code.HasFastBMI2()) {
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(tmp, NZCV::x64_mask);
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code.pext(nzcv_raw, nzcv_raw, tmp);
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code.shl(nzcv_raw, 28);
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} else {
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code.and_(nzcv_raw, NZCV::x64_mask);
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code.imul(nzcv_raw, nzcv_raw, NZCV::from_x64_multiplier);
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code.and_(nzcv_raw, NZCV::arm_mask);
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}
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ctx.reg_alloc.DefineValue(inst, nzcv_raw);
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}
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@ -392,8 +401,14 @@ void A64EmitX64::EmitA64SetNZCVRaw(A64EmitContext& ctx, IR::Inst* inst) {
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const Xbyak::Reg32 nzcv_raw = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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code.shr(nzcv_raw, 28);
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if (code.HasFastBMI2()) {
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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code.mov(tmp, NZCV::x64_mask);
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code.pdep(nzcv_raw, nzcv_raw, tmp);
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} else {
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code.imul(nzcv_raw, nzcv_raw, NZCV::to_x64_multiplier);
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code.and_(nzcv_raw, NZCV::x64_mask);
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}
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code.mov(dword[r15 + offsetof(A64JitState, cpsr_nzcv)], nzcv_raw);
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}
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@ -355,6 +355,10 @@ bool BlockOfCode::HasBMI2() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tBMI2);
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}
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bool BlockOfCode::HasFastBMI2() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tBMI2) && !DoesCpuSupport(Xbyak::util::Cpu::tAMD);
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}
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bool BlockOfCode::HasFMA() const {
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return DoesCpuSupport(Xbyak::util::Cpu::tFMA);
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}
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@ -150,6 +150,7 @@ public:
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bool HasLZCNT() const;
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bool HasBMI1() const;
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bool HasBMI2() const;
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bool HasFastBMI2() const;
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bool HasFMA() const;
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bool HasAVX2() const;
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bool HasAVX512_Skylake() const;
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@ -9,6 +9,7 @@
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#include "backend/x64/block_of_code.h"
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#include "backend/x64/emit_x64.h"
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#include "backend/x64/nzcv_util.h"
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#include "backend/x64/perf_map.h"
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#include "common/assert.h"
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#include "common/bit_util.h"
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@ -158,13 +159,23 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) {
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value |= Common::Bit<29>(args[0].GetImmediateU32()) ? (1 << 8) : 0;
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value |= Common::Bit<28>(args[0].GetImmediateU32()) ? (1 << 0) : 0;
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code.mov(nzcv, value);
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ctx.reg_alloc.DefineValue(inst, nzcv);
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} else if (code.HasFastBMI2()) {
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const Xbyak::Reg32 nzcv = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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const Xbyak::Reg32 tmp = ctx.reg_alloc.ScratchGpr().cvt32();
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code.shr(nzcv, 28);
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code.mov(tmp, NZCV::x64_mask);
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code.pdep(nzcv, nzcv, tmp);
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ctx.reg_alloc.DefineValue(inst, nzcv);
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} else {
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const Xbyak::Reg32 nzcv = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
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// TODO: Optimize
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code.shr(nzcv, 28);
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code.imul(nzcv, nzcv, 0b00010000'10000001);
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code.and_(nzcv.cvt8(), 1);
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code.imul(nzcv, nzcv, NZCV::to_x64_multiplier);
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code.and_(nzcv, NZCV::x64_mask);
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ctx.reg_alloc.DefineValue(inst, nzcv);
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}
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}
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