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thumb32: Implement MOVW

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This commit is contained in:
Lioncash 2021-02-18 23:48:58 -05:00
parent d05c706ff4
commit 5602db88f4
3 changed files with 13 additions and 1 deletions
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2
src/frontend/A32/decoder/thumb32.inc
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@ -73,7 +73,7 @@ INST(thumb32_EOR_imm, "EOR (imm)", "11110v00100Snnnn0vvvdd
// Data Processing (Plain Binary Immediate)
//INST(thumb32_ADR, "ADR", "11110-10000011110---------------")
//INST(thumb32_ADD_imm_2, "ADD (imm)", "11110-100000----0---------------")
//INST(thumb32_MOVW_imm, "MOVW (imm)", "11110-100100----0---------------")
INST(thumb32_MOVW_imm, "MOVW (imm)", "11110i100100iiii0iiiddddiiiiiiii")
//INST(thumb32_ADR, "ADR", "11110-10101011110---------------")
//INST(thumb32_SUB_imm_2, "SUB (imm)", "11110-101010----0---------------")
INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiiddddiiiiiiii")

11
src/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
View file

@ -20,4 +20,15 @@ bool ThumbTranslatorVisitor::thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3,
return true;
}
bool ThumbTranslatorVisitor::thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC) {
return UnpredictableInstruction();
}
const IR::U32 imm = ir.Imm32(concatenate(imm4, imm1, imm3, imm8).ZeroExtend());
ir.SetRegister(d, imm);
return true;
}
} // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_thumb.h
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@ -161,6 +161,7 @@ struct ThumbTranslatorVisitor final {
// thumb32 data processing (plain binary immediate) instructions.
bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
// thumb32 miscellaneous control instructions
bool thumb32_UDF();