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A64: Implement URSRA (vector)

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Lioncash 2018-04-04 08:46:56 -04:00 committed by MerryMage
parent 8afdf4b23d
commit 56803f5203
2 changed files with 28 additions and 4 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -805,7 +805,7 @@ INST(SSHLL, "SSHLL, SSHLL2", "0Q001
INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd") INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd") INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd") INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd") INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd") //INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
//INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd") //INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd")
//INST(SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd") //INST(SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd")

30
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
View file

@ -139,7 +139,13 @@ bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
return true; return true;
} }
static void UnsignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { enum class UnsignedRoundingShiftExtraBehavior {
None,
Accumulate
};
static void UnsignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
UnsignedRoundingShiftExtraBehavior behavior) {
const size_t datasize = Q ? 128 : 64; const size_t datasize = Q ? 128 : 64;
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend()); const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
@ -150,7 +156,12 @@ static void UnsignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh
const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(operand, round_const), round_const); const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(operand, round_const), round_const);
const IR::U128 result = v.ir.VectorLogicalShiftRight(esize, operand, shift_amount); const IR::U128 result = v.ir.VectorLogicalShiftRight(esize, operand, shift_amount);
const IR::U128 corrected_result = v.ir.VectorSub(esize, result, round_correction); IR::U128 corrected_result = v.ir.VectorSub(esize, result, round_correction);
if (behavior == UnsignedRoundingShiftExtraBehavior::Accumulate) {
const IR::U128 accumulator = v.V(datasize, Vd);
corrected_result = v.ir.VectorAdd(esize, accumulator, corrected_result);
}
v.V(datasize, Vd, corrected_result); v.V(datasize, Vd, corrected_result);
} }
@ -164,7 +175,20 @@ bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd
return ReservedValue(); return ReservedValue();
} }
UnsignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd); UnsignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd, UnsignedRoundingShiftExtraBehavior::None);
return true;
}
bool TranslatorVisitor::URSRA_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();
}
if (!Q && immh.Bit<3>()) {
return ReservedValue();
}
UnsignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd, UnsignedRoundingShiftExtraBehavior::Accumulate);
return true; return true;
} }