A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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MerryMage
parent
d040920727
commit
56bc7825ef
4 changed files with 102 additions and 20 deletions
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@ -83,6 +83,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/load_store_multiple_structures.cpp
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frontend/A64/translate/impl/load_store_register_immediate.cpp
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frontend/A64/translate/impl/load_store_register_pair.cpp
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frontend/A64/translate/impl/load_store_register_register_offset.cpp
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frontend/A64/translate/impl/load_store_register_unprivileged.cpp
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frontend/A64/translate/impl/move_wide.cpp
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frontend/A64/translate/impl/simd_aes.cpp
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@ -239,18 +239,10 @@ INST(LDTRSW, "LDTRSW", "10111
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//INST(LDAPR, "LDAPR", "1-11100010111111110000nnnnnttttt")
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// Loads and stores - Load/Store register (register offset)
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//INST(STRB_reg, "STRB (register)", "00111000001mmmmmxxxS10nnnnnttttt")
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//INST(LDRB_reg, "LDRB (register)", "00111000011mmmmmxxxS10nnnnnttttt")
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//INST(LDRSB_reg, "LDRSB (register)", "001110001-1mmmmmxxxS10nnnnnttttt")
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INST(STRx_reg, "STRx (register)", "zz111000o01mmmmmxxxS10nnnnnttttt")
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INST(LDRx_reg, "LDRx (register)", "zz111000o11mmmmmxxxS10nnnnnttttt")
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//INST(STR_reg_fpsimd, "STR (register, SIMD&FP)", "zz111100-01mmmmmxxxS10nnnnnttttt")
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//INST(LDR_reg_fpsimd, "LDR (register, SIMD&FP)", "zz111100-11mmmmmxxxS10nnnnnttttt")
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//INST(STRH_reg, "STRH (register)", "01111000001mmmmmxxxS10nnnnnttttt")
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//INST(LDRH_reg, "LDRH (register)", "01111000011mmmmmxxxS10nnnnnttttt")
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//INST(LDRSH_reg, "LDRSH (register)", "011110001-1mmmmmxxxS10nnnnnttttt")
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//INST(STR_reg_gen, "STR (register)", "1-111000001mmmmmxxxS10nnnnnttttt")
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//INST(LDR_reg_gen, "LDR (register)", "1-111000011mmmmmxxxS10nnnnnttttt")
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//INST(LDRSW_reg, "LDRSW (register)", "10111000101mmmmmxxxS10nnnnnttttt")
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//INST(PRFM_reg, "PRFM (register)", "11111000101mmmmmxxxS10nnnnnttttt")
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// Loads and stores - Load/Store register (pointer authentication)
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//INST(LDRA, "LDRAA, LDRAB", "11111000MS1iiiiiiiiiW1nnnnnttttt")
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@ -293,18 +293,10 @@ struct TranslatorVisitor final {
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bool LDAPR(Reg Rn, Reg Rt);
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// Loads and stores - Load/Store register (register offset)
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bool STRB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDRB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDRSB_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool STR_reg_fpsimd(Imm<2> size, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt);
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bool LDR_reg_fpsimd(Imm<2> size, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt);
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bool STRH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDRH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDRSH_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool STR_reg_gen(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDR_reg_gen(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool LDRSW_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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bool PRFM_reg(Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt);
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// Loads and stores - Load/Store register (pointer authentication)
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bool LDRA(bool M, bool S, Imm<9> imm9, bool W, Reg Rn, Reg Rt);
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@ -0,0 +1,97 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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static bool SharedDecodeAndOperation(TranslatorVisitor& tv, IREmitter& ir, size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1, Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Reg Rt) {
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// Shared Decode
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const AccType acctype = AccType::NORMAL;
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MemOp memop;
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size_t regsize = 64;
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bool signed_ = false;
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if (opc_1 == 0) {
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memop = opc_0 == 1 ? MemOp::LOAD : MemOp::STORE;
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regsize = size == 0b11 ? 64 : 32;
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signed_ = false;
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} else if (size == 0b11) {
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memop = MemOp::PREFETCH;
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if (opc_0 == 1) {
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return tv.UnallocatedEncoding();
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}
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} else {
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memop = MemOp::LOAD;
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if (size == 0b10 && opc_0 == 1) {
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return tv.UnallocatedEncoding();
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}
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regsize = opc_0 == 1 ? 32 : 64;
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signed_ = true;
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}
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const size_t datasize = 8 << scale;
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// Operation
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const IR::U64 offset = tv.ExtendReg(64, Rm, option, shift);
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IR::U64 address;
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if (Rn == Reg::SP) {
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// TODO: Check SP alignment
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address = tv.SP(64);
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} else {
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address = tv.X(64, Rn);
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}
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address = ir.Add(address, offset);
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switch (memop) {
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case MemOp::STORE: {
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IR::UAny data = tv.X(datasize, Rt);
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tv.Mem(address, datasize / 8, acctype, data);
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break;
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}
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case MemOp::LOAD: {
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IR::UAny data = tv.Mem(address, datasize / 8, acctype);
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if (signed_) {
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tv.X(regsize, Rt, tv.SignExtend(data, regsize));
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} else {
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tv.X(regsize, Rt, tv.ZeroExtend(data, regsize));
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}
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break;
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}
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case MemOp::PREFETCH:
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// TODO: Prefetch
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break;
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default:
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UNREACHABLE();
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}
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return true;
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}
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bool TranslatorVisitor::STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt) {
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const Imm<1> opc_0{0};
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const size_t scale = size.ZeroExtend<size_t>();
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const u8 shift = S ? static_cast<u8>(scale) : 0;
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if (!option.Bit<1>()) {
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return UnallocatedEncoding();
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}
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return SharedDecodeAndOperation(*this, ir, scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt);
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}
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bool TranslatorVisitor::LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt) {
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const Imm<1> opc_0{1};
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const size_t scale = size.ZeroExtend<size_t>();
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const u8 shift = S ? static_cast<u8>(scale) : 0;
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if (!option.Bit<1>()) {
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return UnallocatedEncoding();
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}
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return SharedDecodeAndOperation(*this, ir, scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt);
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}
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} // namespace Dynarmic::A64
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