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ir_emitter: Remove overloads

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Having overloads made explicit casting necesssary for these functions when
using types like UAny.
This commit is contained in:
MerryMage 2018-04-03 22:26:29 +01:00
parent 83ff7a43d1
commit 575590d18d
6 changed files with 95 additions and 184 deletions
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12
src/frontend/A32/translate/translate_arm/coprocessor.cpp
View file

@ -38,9 +38,9 @@ bool ArmTranslatorVisitor::arm_LDC(Cond cond, bool p, bool u, bool d, bool w, Re
// LDC{2}{L} <coproc_no>, <CRd>, [<Rn>], #+/-<imm32>
// LDC{2}{L} <coproc_no>, <CRd>, [<Rn>], <imm8>
if (two || ConditionPassed(cond)) {
auto reg_n = ir.GetRegister(n);
auto offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
auto address = index ? offset_address : reg_n;
const IR::U32 reg_n = ir.GetRegister(n);
const IR::U32 offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
const IR::U32 address = index ? offset_address : reg_n;
ir.CoprocLoadWords(coproc_no, two, d, CRd, address, has_option, imm8);
if (wback) {
ir.SetRegister(n, offset_address);
@ -134,9 +134,9 @@ bool ArmTranslatorVisitor::arm_STC(Cond cond, bool p, bool u, bool d, bool w, Re
// STC{2}{L} <coproc>, <CRd>, [<Rn>], #+/-<imm32>
// STC{2}{L} <coproc>, <CRd>, [<Rn>], <imm8>
if (two || ConditionPassed(cond)) {
auto reg_n = ir.GetRegister(n);
auto offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
auto address = index ? offset_address : reg_n;
const IR::U32 reg_n = ir.GetRegister(n);
const IR::U32 offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
const IR::U32 address = index ? offset_address : reg_n;
ir.CoprocStoreWords(coproc_no, two, d, CRd, address, has_option, imm8);
if (wback) {
ir.SetRegister(n, offset_address);

4
src/frontend/A32/translate/translate_arm/load_store.cpp
View file

@ -45,8 +45,8 @@ static IR::U32 GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR:
const bool add = U;
const bool wback = !P || W;
const auto offset_addr = add ? ir.Add(ir.GetRegister(n), offset) : ir.Sub(ir.GetRegister(n), offset);
const auto address = index ? offset_addr : ir.GetRegister(n);
const IR::U32 offset_addr = add ? ir.Add(ir.GetRegister(n), offset) : ir.Sub(ir.GetRegister(n), offset);
const IR::U32 address = index ? offset_addr : ir.GetRegister(n);
if (wback) {
ir.SetRegister(n, offset_addr);

145
src/frontend/A32/translate/translate_arm/multiply.cpp
View file

@ -151,13 +151,13 @@ bool ArmTranslatorVisitor::arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool
if (dLo == dHi)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
const IR::U32 m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto product = ir.SignExtendWordToLong(ir.Mul(n16, m16));
const IR::U64 product = ir.SignExtendWordToLong(ir.Mul(n16, m16));
auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
auto result = ir.Add(product, addend);
ir.SetRegister(dLo, ir.LeastSignificantWord(result));
@ -170,13 +170,13 @@ bool ArmTranslatorVisitor::arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bo
if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
const IR::U32 m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto product = ir.Mul(n16, m16);
const IR::U32 product = ir.Mul(n16, m16);
auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
ir.SetRegister(d, result_overflow.result);
ir.OrQFlag(result_overflow.overflow);
@ -188,13 +188,13 @@ bool ArmTranslatorVisitor::arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, R
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
const IR::U32 m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto result = ir.Mul(n16, m16);
const IR::U32 result = ir.Mul(n16, m16);
ir.SetRegister(d, result);
}
return true;
@ -206,11 +206,11 @@ bool ArmTranslatorVisitor::arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Re
if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
auto m32 = ir.GetRegister(m);
const IR::U64 n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
IR::U32 m32 = ir.GetRegister(m);
if (M)
m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
auto m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32)));
const IR::U64 m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32)));
auto product = ir.LeastSignificantWord(ir.LogicalShiftRight(ir.Mul(n32, m16), ir.Imm8(16)));
auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
ir.SetRegister(d, result_overflow.result);
@ -223,11 +223,11 @@ bool ArmTranslatorVisitor::arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
auto m32 = ir.GetRegister(m);
const IR::U64 n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
IR::U32 m32 = ir.GetRegister(m);
if (M)
m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
auto m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32)));
const IR::U64 m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32)));
auto result = ir.LogicalShiftRight(ir.Mul(n32, m16), ir.Imm8(16));
ir.SetRegister(d, ir.LeastSignificantWord(result));
}
@ -294,17 +294,17 @@ bool ArmTranslatorVisitor::arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
IR::U32 m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U32 n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
IR::U32 m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
if (M)
std::swap(m_lo, m_hi);
auto product_lo = ir.Mul(n_lo, m_lo);
auto product_hi = ir.Mul(n_hi, m_hi);
auto addend = ir.GetRegister(a);
const IR::U32 product_lo = ir.Mul(n_lo, m_lo);
const IR::U32 product_hi = ir.Mul(n_hi, m_hi);
const IR::U32 addend = ir.GetRegister(a);
auto result_overflow = ir.AddWithCarry(product_lo, product_hi, ir.Imm1(0));
ir.OrQFlag(result_overflow.overflow);
result_overflow = ir.AddWithCarry(result_overflow.result, addend, ir.Imm1(0));
@ -320,16 +320,16 @@ bool ArmTranslatorVisitor::arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M
if (dLo == dHi)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
IR::U32 m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U32 n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
IR::U32 m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
if (M)
std::swap(m_lo, m_hi);
auto product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
auto product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
const IR::U64 product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
const IR::U64 product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
auto result = ir.Add(ir.Add(product_lo, product_hi), addend);
ir.SetRegister(dLo, ir.LeastSignificantWord(result));
@ -344,18 +344,19 @@ bool ArmTranslatorVisitor::arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
IR::U32 m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U32 n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
IR::U32 m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
if (M)
std::swap(m_lo, m_hi);
auto product_lo = ir.Mul(n_lo, m_lo);
auto product_hi = ir.Mul(n_hi, m_hi);
auto addend = ir.GetRegister(a);
auto result_overflow = ir.AddWithCarry(ir.Sub(product_lo, product_hi), addend, ir.Imm1(0));
const IR::U32 product_lo = ir.Mul(n_lo, m_lo);
const IR::U32 product_hi = ir.Mul(n_hi, m_hi);
const IR::U32 addend = ir.GetRegister(a);
const IR::U32 product = ir.Sub(product_lo, product_hi);
auto result_overflow = ir.AddWithCarry(product, addend, ir.Imm1(0));
ir.SetRegister(d, result_overflow.result);
ir.OrQFlag(result_overflow.overflow);
}
@ -368,16 +369,16 @@ bool ArmTranslatorVisitor::arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M
if (dLo == dHi)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
IR::U32 m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U32 n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
IR::U32 m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
if (M)
std::swap(m_lo, m_hi);
auto product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
auto product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
const IR::U64 product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
const IR::U64 product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
auto result = ir.Add(ir.Sub(product_lo, product_hi), addend);
ir.SetRegister(dLo, ir.LeastSignificantWord(result));
@ -390,16 +391,16 @@ bool ArmTranslatorVisitor::arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
IR::U32 m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U32 n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
IR::U32 m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
if (M)
std::swap(m_lo, m_hi);
auto product_lo = ir.Mul(n_lo, m_lo);
auto product_hi = ir.Mul(n_hi, m_hi);
const IR::U32 product_lo = ir.Mul(n_lo, m_lo);
const IR::U32 product_hi = ir.Mul(n_hi, m_hi);
auto result_overflow = ir.AddWithCarry(product_lo, product_hi, ir.Imm1(0));
ir.SetRegister(d, result_overflow.result);
ir.OrQFlag(result_overflow.overflow);
@ -411,16 +412,16 @@ bool ArmTranslatorVisitor::arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto n32 = ir.GetRegister(n);
auto m32 = ir.GetRegister(m);
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
IR::U32 m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U32 n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
IR::U32 m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
if (M)
std::swap(m_lo, m_hi);
auto product_lo = ir.Mul(n_lo, m_lo);
auto product_hi = ir.Mul(n_hi, m_hi);
const IR::U32 product_lo = ir.Mul(n_lo, m_lo);
const IR::U32 product_hi = ir.Mul(n_hi, m_hi);
auto result = ir.Sub(product_lo, product_hi);
ir.SetRegister(d, result);
}

16
src/frontend/A32/translate/translate_arm/vfp2.cpp
View file

@ -652,9 +652,9 @@ bool ArmTranslatorVisitor::vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool
// VSTM<mode>.F64 <Rn>{!}, <list of double registers>
if (ConditionPassed(cond)) {
auto address = u ? ir.GetRegister(n) : ir.Sub(ir.GetRegister(n), ir.Imm32(imm32));
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
if (w)
ir.SetRegister(n, u ? ir.Add(address, ir.Imm32(imm32)) : address);
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
for (size_t i = 0; i < regs; i++) {
auto value = ir.GetExtendedRegister(d + i);
auto word1 = ir.LeastSignificantWord(value);
@ -688,9 +688,9 @@ bool ArmTranslatorVisitor::vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool
// VSTM<mode>.F32 <Rn>{!}, <list of single registers>
if (ConditionPassed(cond)) {
auto address = u ? ir.GetRegister(n) : ir.Sub(ir.GetRegister(n), ir.Imm32(imm32));
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
if (w)
ir.SetRegister(n, u ? ir.Add(address, ir.Imm32(imm32)) : address);
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
for (size_t i = 0; i < regs; i++) {
auto word = ir.GetExtendedRegister(d + i);
ir.WriteMemory32(address, word);
@ -719,9 +719,9 @@ bool ArmTranslatorVisitor::vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool
// VLDM<mode>.F64 <Rn>{!}, <list of double registers>
if (ConditionPassed(cond)) {
auto address = u ? ir.GetRegister(n) : ir.Sub(ir.GetRegister(n), ir.Imm32(imm32));
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
if (w)
ir.SetRegister(n, u ? ir.Add(address, ir.Imm32(imm32)) : address);
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
for (size_t i = 0; i < regs; i++) {
auto word1 = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));
@ -753,9 +753,9 @@ bool ArmTranslatorVisitor::vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool
// VLDM<mode>.F32 <Rn>{!}, <list of single registers>
if (ConditionPassed(cond)) {
auto address = u ? ir.GetRegister(n) : ir.Sub(ir.GetRegister(n), ir.Imm32(imm32));
auto address = u ? ir.GetRegister(n) : IR::U32(ir.Sub(ir.GetRegister(n), ir.Imm32(imm32)));
if (w)
ir.SetRegister(n, u ? ir.Add(address, ir.Imm32(imm32)) : address);
ir.SetRegister(n, u ? IR::U32(ir.Add(address, ir.Imm32(imm32))) : address);
for (size_t i = 0; i < regs; i++) {
auto word = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));

72
src/frontend/ir/ir_emitter.cpp
View file

@ -217,14 +217,6 @@ U32U64 IREmitter::AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry
}
}
U32 IREmitter::Add(const U32& a, const U32& b) {
return Inst<U32>(Opcode::Add32, a, b, Imm1(0));
}
U64 IREmitter::Add(const U64& a, const U64& b) {
return Inst<U64>(Opcode::Add64, a, b, Imm1(0));
}
U32U64 IREmitter::Add(const U32U64& a, const U32U64& b) {
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
@ -251,14 +243,6 @@ U32U64 IREmitter::SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry
}
}
U32 IREmitter::Sub(const U32& a, const U32& b) {
return Inst<U32>(Opcode::Sub32, a, b, Imm1(1));
}
U64 IREmitter::Sub(const U64& a, const U64& b) {
return Inst<U64>(Opcode::Sub64, a, b, Imm1(1));
}
U32U64 IREmitter::Sub(const U32U64& a, const U32U64& b) {
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
@ -268,14 +252,6 @@ U32U64 IREmitter::Sub(const U32U64& a, const U32U64& b) {
}
}
U32 IREmitter::Mul(const U32& a, const U32& b) {
return Inst<U32>(Opcode::Mul32, a, b);
}
U64 IREmitter::Mul(const U64& a, const U64& b) {
return Inst<U64>(Opcode::Mul64, a, b);
}
U32U64 IREmitter::Mul(const U32U64& a, const U32U64& b) {
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::Mul32, a, b);
@ -292,14 +268,6 @@ U64 IREmitter::SignedMultiplyHigh(const U64& a, const U64& b) {
return Inst<U64>(Opcode::SignedMultiplyHigh64, a, b);
}
U32 IREmitter::UnsignedDiv(const U32& a, const U32& b) {
return Inst<U32>(Opcode::UnsignedDiv32, a, b);
}
U64 IREmitter::UnsignedDiv(const U64& a, const U64& b) {
return Inst<U64>(Opcode::UnsignedDiv64, a, b);
}
U32U64 IREmitter::UnsignedDiv(const U32U64& a, const U32U64& b) {
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::UnsignedDiv32, a, b);
@ -308,14 +276,6 @@ U32U64 IREmitter::UnsignedDiv(const U32U64& a, const U32U64& b) {
return Inst<U64>(Opcode::UnsignedDiv64, a, b);
}
U32 IREmitter::SignedDiv(const U32& a, const U32& b) {
return Inst<U32>(Opcode::SignedDiv32, a, b);
}
U64 IREmitter::SignedDiv(const U64& a, const U64& b) {
return Inst<U64>(Opcode::SignedDiv64, a, b);
}
U32U64 IREmitter::SignedDiv(const U32U64& a, const U32U64& b) {
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::SignedDiv32, a, b);
@ -324,10 +284,6 @@ U32U64 IREmitter::SignedDiv(const U32U64& a, const U32U64& b) {
return Inst<U64>(Opcode::SignedDiv64, a, b);
}
U32 IREmitter::And(const U32& a, const U32& b) {
return Inst<U32>(Opcode::And32, a, b);
}
U32U64 IREmitter::And(const U32U64& a, const U32U64& b) {
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
@ -337,10 +293,6 @@ U32U64 IREmitter::And(const U32U64& a, const U32U64& b) {
}
}
U32 IREmitter::Eor(const U32& a, const U32& b) {
return Inst<U32>(Opcode::Eor32, a, b);
}
U32U64 IREmitter::Eor(const U32U64& a, const U32U64& b) {
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
@ -350,10 +302,6 @@ U32U64 IREmitter::Eor(const U32U64& a, const U32U64& b) {
}
}
U32 IREmitter::Or(const U32& a, const U32& b) {
return Inst<U32>(Opcode::Or32, a, b);
}
U32U64 IREmitter::Or(const U32U64& a, const U32U64& b) {
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {
@ -363,10 +311,6 @@ U32U64 IREmitter::Or(const U32U64& a, const U32U64& b) {
}
}
U32 IREmitter::Not(const U32& a) {
return Inst<U32>(Opcode::Not32, a);
}
U32U64 IREmitter::Not(const U32U64& a) {
if (a.GetType() == Type::U32) {
return Inst<U32>(Opcode::Not32, a);
@ -489,14 +433,6 @@ U64 IREmitter::ByteReverseDual(const U64& a) {
return Inst<U64>(Opcode::ByteReverseDual, a);
}
U32 IREmitter::CountLeadingZeros(const U32& a) {
return Inst<U32>(Opcode::CountLeadingZeros32, a);
}
U64 IREmitter::CountLeadingZeros(const U64& a) {
return Inst<U64>(Opcode::CountLeadingZeros64, a);
}
U32U64 IREmitter::CountLeadingZeros(const U32U64& a) {
if (a.GetType() == IR::Type::U32) {
return Inst<U32>(Opcode::CountLeadingZeros32, a);
@ -505,14 +441,6 @@ U32U64 IREmitter::CountLeadingZeros(const U32U64& a) {
return Inst<U64>(Opcode::CountLeadingZeros64, a);
}
U32 IREmitter::ExtractRegister(const U32& a, const U32& b, const U8& lsb) {
return Inst<U32>(Opcode::ExtractRegister32, a, b, lsb);
}
U64 IREmitter::ExtractRegister(const U64& a, const U64& b, const U8& lsb) {
return Inst<U64>(Opcode::ExtractRegister64, a, b, lsb);
}
U32U64 IREmitter::ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb) {
if (a.GetType() == IR::Type::U32) {
return Inst<U32>(Opcode::ExtractRegister32, a, b, lsb);

18
src/frontend/ir/ir_emitter.h
View file

@ -104,30 +104,16 @@ public:
ResultAndCarryAndOverflow<U32> SubWithCarry(const U32& a, const U32& b, const U1& carry_in);
U32U64 AddWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in);
U32U64 SubWithCarry(const U32U64& a, const U32U64& b, const U1& carry_in);
U32 Add(const U32& a, const U32& b);
U64 Add(const U64& a, const U64& b);
U32U64 Add(const U32U64& a, const U32U64& b);
U32 Sub(const U32& a, const U32& b);
U64 Sub(const U64& a, const U64& b);
U32U64 Sub(const U32U64& a, const U32U64& b);
U32 Mul(const U32& a, const U32& b);
U64 Mul(const U64& a, const U64& b);
U32U64 Mul(const U32U64& a, const U32U64& b);
U64 UnsignedMultiplyHigh(const U64& a, const U64& b);
U64 SignedMultiplyHigh(const U64& a, const U64& b);
U32 UnsignedDiv(const U32& a, const U32& b);
U64 UnsignedDiv(const U64& a, const U64& b);
U32U64 UnsignedDiv(const U32U64& a, const U32U64& b);
U32 SignedDiv(const U32& a, const U32& b);
U64 SignedDiv(const U64& a, const U64& b);
U32U64 SignedDiv(const U32U64& a, const U32U64& b);
U32 And(const U32& a, const U32& b);
U32U64 And(const U32U64& a, const U32U64& b);
U32 Eor(const U32& a, const U32& b);
U32U64 Eor(const U32U64& a, const U32U64& b);
U32 Or(const U32& a, const U32& b);
U32U64 Or(const U32U64& a, const U32U64& b);
U32 Not(const U32& a);
U32U64 Not(const U32U64& a);
U32 SignExtendToWord(const UAny& a);
U64 SignExtendToLong(const UAny& a);
@ -145,11 +131,7 @@ public:
U32 ByteReverseWord(const U32& a);
U16 ByteReverseHalf(const U16& a);
U64 ByteReverseDual(const U64& a);
U32 CountLeadingZeros(const U32& a);
U64 CountLeadingZeros(const U64& a);
U32U64 CountLeadingZeros(const U32U64& a);
U32 ExtractRegister(const U32& a, const U32& b, const U8& lsb);
U64 ExtractRegister(const U64& a, const U64& b, const U8& lsb);
U32U64 ExtractRegister(const U32U64& a, const U32U64& b, const U8& lsb);
ResultAndOverflow<U32> SignedSaturatedAdd(const U32& a, const U32& b);