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Move SEL from status_register_access to misc

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This commit is contained in:
MerryMage 2017-04-25 13:57:27 +01:00
parent 50bb317104
commit 599a613fea
2 changed files with 27 additions and 27 deletions
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27
src/frontend/translate/translate_arm/misc.cpp
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@ -18,5 +18,32 @@ bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
return true;
}
bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
if (n == Reg::PC || d == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto ge = ir.GetGEFlags();
// Perform some arithmetic to expand 0bXYZW into 0bXXXXXXXXYYYYYYYYZZZZZZZZWWWWWWWW => 0xXXYYZZWW
// The logic behind this is as follows:
// 0000 0000 0000 0000 | 0000 0000 0000 xyzw
// 0000 000x yzw0 00xy | zw00 0xyz w000 xyzw (x * 0x00204081)
// 0000 000x 0000 000y | 0000 000z 0000 000w (x & 0x01010101)
// xxxx xxxx yyyy yyyy | zzzz zzzz wwww wwww (x * 0xff)
auto x2 = ir.Mul(ge, ir.Imm32(0x00204081));
auto x3 = ir.And(x2, ir.Imm32(0x01010101));
auto mask = ir.Mul(x3, ir.Imm32(0xFF));
auto to = ir.GetRegister(m);
auto from = ir.GetRegister(n);
auto result = ir.Or(ir.And(from, mask), ir.And(to, ir.Not(mask)));
ir.SetRegister(d, result);
}
return true;
}
} // namespace Arm
} // namespace Dynarmic

27
src/frontend/translate/translate_arm/status_register_access.cpp
View file

@ -77,32 +77,5 @@ bool ArmTranslatorVisitor::arm_SRS() {
return InterpretThisInstruction();
}
bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
if (n == Reg::PC || d == Reg::PC || m == Reg::PC)
return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto ge = ir.GetGEFlags();
// Perform some arithmetic to expand 0bXYZW into 0bXXXXXXXXYYYYYYYYZZZZZZZZWWWWWWWW => 0xXXYYZZWW
// The logic behind this is as follows:
// 0000 0000 0000 0000 | 0000 0000 0000 xyzw
// 0000 000x yzw0 00xy | zw00 0xyz w000 xyzw (x * 0x00204081)
// 0000 000x 0000 000y | 0000 000z 0000 000w (x & 0x01010101)
// xxxx xxxx yyyy yyyy | zzzz zzzz wwww wwww (x * 0xff)
auto x2 = ir.Mul(ge, ir.Imm32(0x00204081));
auto x3 = ir.And(x2, ir.Imm32(0x01010101));
auto mask = ir.Mul(x3, ir.Imm32(0xFF));
auto to = ir.GetRegister(m);
auto from = ir.GetRegister(n);
auto result = ir.Or(ir.And(from, mask), ir.And(to, ir.Not(mask)));
ir.SetRegister(d, result);
}
return true;
}
} // namespace Arm
} // namespace Dynarmic