Squashed 'externals/xbyak/' changes from 913099fc8..88f2f771f

88f2f771f Merge branch 'dev'
8623616e0 v6.61
1b911598d mingw uses __thread instead of __declspec(thread)
d224701f4 fix movzx eax, ah on 64bit and test it
1c35e34ab Merge branch 'dev'
4fb0e58aa test of cpuid
913c798ff update doc
8f6dee319 v6.60.2
21419721e Merge branch 'Wunkolo-standalone-cpuid' into dev
1b2e7c7da Fix detection of `GFNI`,`VAES`, and `VPCLMULQDQ`

git-subtree-dir: externals/xbyak
git-subtree-split: 88f2f771f179a3d856ecd0b07a20598bd06ba21d
This commit is contained in:
Merry 2022-07-31 17:50:57 +01:00
parent 9af5f5908c
commit 5b6e3d8b54
38 changed files with 94 additions and 13 deletions

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@ -1,6 +1,6 @@
cmake_minimum_required(VERSION 2.6...3.0.2) cmake_minimum_required(VERSION 2.6...3.0.2)
project(xbyak LANGUAGES CXX VERSION 6.60.1) project(xbyak LANGUAGES CXX VERSION 6.61)
file(GLOB headers xbyak/*.h) file(GLOB headers xbyak/*.h)

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@ -1,5 +1,7 @@
# History # History
* 2022/Jul/29 ver 6.61 fix exception of movzx eax, ah in 64-bit mode
* 2022/Jun/16 ver 6.60.2 fix detection of GFNI, VAES, and VPCLMULQDQ
* 2022/Jun/15 ver 6.60.1 fix link error of Xbyak::util::Cpu on Visual Studio with /O0 option * 2022/Jun/15 ver 6.60.1 fix link error of Xbyak::util::Cpu on Visual Studio with /O0 option
* 2022/Jun/06 ver 6.60 change the version format to avoid it going backward * 2022/Jun/06 ver 6.60 change the version format to avoid it going backward
* 2022/Jun/01 ver 6.06 refactor Cpu::Type class and improve MmapAllocator when XBYAK_USE_MEMFD is defined. * 2022/Jun/01 ver 6.06 refactor Cpu::Type class and improve MmapAllocator when XBYAK_USE_MEMFD is defined.

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@ -5,7 +5,7 @@
project( project(
'xbyak', 'xbyak',
'cpp', 'cpp',
version: '6.60.1', version: '6.61',
license: 'BSD-3-Clause', license: 'BSD-3-Clause',
default_options: 'b_ndebug=if-release' default_options: 'b_ndebug=if-release'
) )

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@ -1,5 +1,5 @@
# Xbyak 6.60.1 [![Badge Build]][Build Status] # Xbyak 6.61 [![Badge Build]][Build Status]
*A C++ JIT assembler for x86 (IA32), x64 (AMD64, x86-64)* *A C++ JIT assembler for x86 (IA32), x64 (AMD64, x86-64)*

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@ -1,5 +1,5 @@
C++用x86(IA-32), x64(AMD64, x86-64) JITアセンブラ Xbyak 6.60.1 C++用x86(IA-32), x64(AMD64, x86-64) JITアセンブラ Xbyak 6.61
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
◎概要 ◎概要
@ -400,6 +400,8 @@ sample/{echo,hello}.bfは http://www.kmonos.net/alang/etc/brainfuck.php から
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
◎履歴 ◎履歴
2022/07/29 ver 6.61 movzx eax, ahがエラーになるのを修正
2022/06/16 ver 6.60.2 GFNI, VAES, VPCLMULQDQの判定修正
2022/06/15 ver 6.60.1 Visual Studio /O0でXbyak::util::Cpuがリンクエラーになるのに対応 2022/06/15 ver 6.60.1 Visual Studio /O0でXbyak::util::Cpuがリンクエラーになるのに対応
2022/06/06 ver 6.60 バージョンのつけ方を数値が戻らないように変更 2022/06/06 ver 6.60 バージョンのつけ方を数値が戻らないように変更
2022/06/01 ver 6.06 Cpu::TypeクラスのリファクタリングとXBYAK_USE_MEMFDが定義されたときのMmapAllocatorの改善 2022/06/01 ver 6.06 Cpu::TypeクラスのリファクタリングとXBYAK_USE_MEMFDが定義されたときのMmapAllocatorの改善

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sample/cpuid/adl.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx_vnni waitpkg clflushopt cldemote movdiri movdir64b

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sample/cpuid/bdw.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap f16c movbe

2
sample/cpuid/clx.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap f16c movbe avx512f avx512dq avx512cd avx512bw avx512vl avx512_vnni clflushopt

2
sample/cpuid/cnl.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi clflushopt

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sample/cpuid/cpuid.sh Executable file
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@ -0,0 +1,11 @@
#!/bin/bash
make -C ../ test_util64
cpus=(p4p mrm pnr nhm wsm snb ivb hsw bdw slt slm glm glp tnt skl cnl icl skx clx cpx icx knl knm tgl adl spr)
for cpu in ${cpus[@]} ; do
echo $cpu
~/bin/sde -$cpu -- ../test_util64 -cpuid > tmp.txt
diff tmp.txt $cpu.txt
done

2
sample/cpuid/cpx.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap f16c movbe avx512f avx512dq avx512cd avx512bw avx512vl avx512_vnni avx512_bf16 clflushopt

2
sample/cpuid/glm.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq enh_rep rdrand rdseed smap sha movbe clflushopt

2
sample/cpuid/glp.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq enh_rep rdrand rdseed smap sha movbe clflushopt

2
sample/cpuid/hsw.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt enh_rep rdrand f16c movbe

2
sample/cpuid/icl.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq clflushopt

2
sample/cpuid/icx.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq clflushopt

2
sample/cpuid/ivb.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx enh_rep rdrand f16c

2
sample/cpuid/knl.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed prefetchwt1 f16c movbe avx512f avx512pf avx512er avx512cd

2
sample/cpuid/knm.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed prefetchwt1 f16c movbe avx512f avx512pf avx512er avx512cd avx512_4vnniw avx512_4fmaps avx512_vpopcntdq

2
sample/cpuid/mrm.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3

2
sample/cpuid/nhm.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt rdtscp

2
sample/cpuid/p4p.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3

2
sample/cpuid/pnr.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41

2
sample/cpuid/skl.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap f16c movbe clflushopt

2
sample/cpuid/skx.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap f16c movbe avx512f avx512dq avx512cd avx512bw avx512vl clflushopt

2
sample/cpuid/slm.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp pclmulqdq prefetchw enh_rep rdrand movbe

2
sample/cpuid/slt.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 movbe

2
sample/cpuid/snb.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx

2
sample/cpuid/spr.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_bf16 avx512_vp2intersect amx(tile) amx(int8) amx(bf16) avx_vnni avx512_fp16 waitpkg clflushopt cldemote movdiri movdir64b

2
sample/cpuid/tgl.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_vp2intersect clflushopt movdiri movdir64b

2
sample/cpuid/tmp.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_bf16 avx512_vp2intersect amx(tile) amx(int8) amx(bf16) avx_vnni avx512_fp16 waitpkg clflushopt cldemote movdiri movdir64b

2
sample/cpuid/tnt.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp osxsave(xgetvb) pclmulqdq enh_rep rdrand rdseed smap sha movbe clflushopt

10
sample/cpuid/update-txt.sh Executable file
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@ -0,0 +1,10 @@
#!/bin/bash
make -C ../ test_util64
cpus=(p4p mrm pnr nhm wsm snb ivb hsw bdw slt slm glm glp tnt skl cnl icl skx clx cpx icx knl knm tgl adl spr)
for cpu in ${cpus[@]} ; do
echo $cpu
~/bin/sde -$cpu -- ../test_util64 -cpuid > $cpu.txt
done

2
sample/cpuid/wsm.txt Normal file
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@ -0,0 +1,2 @@
vendor intel
mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp pclmulqdq

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@ -1317,6 +1317,7 @@ class Test {
put(p, REG64, REG16|REG8|MEM8|MEM16); put(p, REG64, REG16|REG8|MEM8|MEM16);
put(p, REG32, REG16|REG8|MEM8|MEM16); put(p, REG32, REG16|REG8|MEM8|MEM16);
put(p, REG16, REG8|MEM8); put(p, REG16, REG8|MEM8);
put(p, "eax, ah");
} }
} }
#ifdef XBYAK64 #ifdef XBYAK64

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@ -77,7 +77,11 @@
#endif #endif
#include <windows.h> #include <windows.h>
#include <malloc.h> #include <malloc.h>
#ifdef _MSC_VER
#define XBYAK_TLS __declspec(thread) #define XBYAK_TLS __declspec(thread)
#else
#define XBYAK_TLS __thread
#endif
#elif defined(__GNUC__) #elif defined(__GNUC__)
#include <unistd.h> #include <unistd.h>
#include <sys/mman.h> #include <sys/mman.h>
@ -144,7 +148,7 @@ namespace Xbyak {
enum { enum {
DEFAULT_MAX_CODE_SIZE = 4096, DEFAULT_MAX_CODE_SIZE = 4096,
VERSION = 0x6601 /* 0xABCD = A.BC(.D) */ VERSION = 0x6610 /* 0xABCD = A.BC(.D) */
}; };
#ifndef MIE_INTEGER_TYPE_DEFINED #ifndef MIE_INTEGER_TYPE_DEFINED
@ -2187,9 +2191,6 @@ private:
{ {
if (op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION) if (op.isBit(32)) XBYAK_THROW(ERR_BAD_COMBINATION)
int w = op.isBit(16); int w = op.isBit(16);
#ifdef XBYAK64
if (op.isHigh8bit()) XBYAK_THROW(ERR_BAD_COMBINATION)
#endif
bool cond = reg.isREG() && (reg.getBit() > op.getBit()); bool cond = reg.isREG() && (reg.getBit() > op.getBit());
opModRM(reg, op, cond && op.isREG(), cond && op.isMEM(), 0x0F, code | w); opModRM(reg, op, cond && op.isREG(), cond && op.isMEM(), 0x0F, code | w);
} }

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@ -1,4 +1,4 @@
const char *getVersionString() const { return "6.60.1"; } const char *getVersionString() const { return "6.61"; }
void adc(const Operand& op, uint32_t imm) { opRM_I(op, imm, 0x10, 2); } void adc(const Operand& op, uint32_t imm) { opRM_I(op, imm, 0x10, 2); }
void adc(const Operand& op1, const Operand& op2) { opRM_RM(op1, op2, 0x10); } void adc(const Operand& op1, const Operand& op2) { opRM_RM(op1, op2, 0x10); }
void adcx(const Reg32e& reg, const Operand& op) { opGen(reg, op, 0xF6, 0x66, isREG32_REG32orMEM, NONE, 0x38); } void adcx(const Reg32e& reg, const Operand& op) { opGen(reg, op, 0xF6, 0x66, isREG32_REG32orMEM, NONE, 0x38); }

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@ -506,9 +506,6 @@ public:
if (EBX & (1U << 31)) type_ |= tAVX512VL; if (EBX & (1U << 31)) type_ |= tAVX512VL;
if (ECX & (1U << 1)) type_ |= tAVX512_VBMI; if (ECX & (1U << 1)) type_ |= tAVX512_VBMI;
if (ECX & (1U << 6)) type_ |= tAVX512_VBMI2; if (ECX & (1U << 6)) type_ |= tAVX512_VBMI2;
if (ECX & (1U << 8)) type_ |= tGFNI;
if (ECX & (1U << 9)) type_ |= tVAES;
if (ECX & (1U << 10)) type_ |= tVPCLMULQDQ;
if (ECX & (1U << 11)) type_ |= tAVX512_VNNI; if (ECX & (1U << 11)) type_ |= tAVX512_VNNI;
if (ECX & (1U << 12)) type_ |= tAVX512_BITALG; if (ECX & (1U << 12)) type_ |= tAVX512_BITALG;
if (ECX & (1U << 14)) type_ |= tAVX512_VPOPCNTDQ; if (ECX & (1U << 14)) type_ |= tAVX512_VPOPCNTDQ;
@ -537,6 +534,9 @@ public:
if (EBX & (1U << 29)) type_ |= tSHA; if (EBX & (1U << 29)) type_ |= tSHA;
if (ECX & (1U << 0)) type_ |= tPREFETCHWT1; if (ECX & (1U << 0)) type_ |= tPREFETCHWT1;
if (ECX & (1U << 5)) type_ |= tWAITPKG; if (ECX & (1U << 5)) type_ |= tWAITPKG;
if (ECX & (1U << 8)) type_ |= tGFNI;
if (ECX & (1U << 9)) type_ |= tVAES;
if (ECX & (1U << 10)) type_ |= tVPCLMULQDQ;
if (ECX & (1U << 25)) type_ |= tCLDEMOTE; if (ECX & (1U << 25)) type_ |= tCLDEMOTE;
if (ECX & (1U << 27)) type_ |= tMOVDIRI; if (ECX & (1U << 27)) type_ |= tMOVDIRI;
if (ECX & (1U << 28)) type_ |= tMOVDIR64B; if (ECX & (1U << 28)) type_ |= tMOVDIR64B;