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A64: Implement FCADD

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Lioncash 2019-03-02 21:54:41 -05:00 committed by MerryMage
parent 20fabc5083
commit 5ce17574f9
2 changed files with 52 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -606,7 +606,7 @@ INST(INS_elt, "INS (element)", "01101
INST(SDOT_vec, "SDOT (vector)", "0Q001110zz0mmmmm100101nnnnnddddd") INST(SDOT_vec, "SDOT (vector)", "0Q001110zz0mmmmm100101nnnnnddddd")
INST(UDOT_vec, "UDOT (vector)", "0Q101110zz0mmmmm100101nnnnnddddd") INST(UDOT_vec, "UDOT (vector)", "0Q101110zz0mmmmm100101nnnnnddddd")
//INST(FCMLA_vec, "FCMLA", "0Q101110zz0mmmmm110rr1nnnnnddddd") //INST(FCMLA_vec, "FCMLA", "0Q101110zz0mmmmm110rr1nnnnnddddd")
//INST(FCADD_vec, "FCADD", "0Q101110zz0mmmmm111r01nnnnnddddd") INST(FCADD_vec, "FCADD", "0Q101110zz0mmmmm111r01nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Two-register misc // Data Processing - FP and SIMD - SIMD Two-register misc
INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd") INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd")

51
src/frontend/A64/translate/impl/simd_three_same_extra.cpp
View file

@ -53,4 +53,55 @@ bool TranslatorVisitor::UDOT_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return DotProduct(*this, Q, size, Vm, Vn, Vd, &IREmitter::ZeroExtendToWord); return DotProduct(*this, Q, size, Vm, Vn, Vd, &IREmitter::ZeroExtendToWord);
} }
bool TranslatorVisitor::FCADD_vec(bool Q, Imm<2> size, Vec Vm, Imm<1> rot, Vec Vn, Vec Vd) {
if (size == 0) {
return UnallocatedEncoding();
}
if (!Q && size == 0b11) {
return UnallocatedEncoding();
}
const size_t esize = 8U << size.ZeroExtend();
// TODO: Currently we don't support half-precision floating point
if (esize == 16) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
const size_t num_elements = datasize / esize;
const size_t num_iterations = num_elements / 2;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
IR::U128 result = ir.ZeroVector();
IR::U32U64 element1;
IR::U32U64 element3;
for (size_t e = 0; e < num_iterations; ++e) {
const size_t first = e * 2;
const size_t second = first + 1;
if (rot == 0) {
element1 = ir.FPNeg(ir.VectorGetElement(esize, operand2, second));
element3 = ir.VectorGetElement(esize, operand2, first);
} else if (rot == 1) {
element1 = ir.VectorGetElement(esize, operand2, second);
element3 = ir.FPNeg(ir.VectorGetElement(esize, operand2, first));
}
const IR::U32U64 operand1_elem1 = ir.VectorGetElement(esize, operand1, first);
const IR::U32U64 operand1_elem3 = ir.VectorGetElement(esize, operand1, second);
result = ir.VectorSetElement(esize, result, first,
ir.FPAdd(operand1_elem1, element1, true));
result = ir.VectorSetElement(esize, result, second,
ir.FPAdd(operand1_elem3, element3, true));
}
ir.SetQ(Vd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64