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frontend/ir: Add opcodes for vector square roots

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Lioncash 2019-03-04 12:43:24 -05:00 committed by MerryMage
parent 36027ebef5
commit 5cf1478620
5 changed files with 28 additions and 0 deletions
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12
src/backend/x64/emit_x64_vector_floating_point.cpp
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@ -1300,6 +1300,18 @@ void EmitX64::EmitFPVectorRSqrtStepFused64(EmitContext& ctx, IR::Inst* inst) {
EmitRSqrtStepFused<64>(code, ctx, inst);
}
void EmitX64::EmitFPVectorSqrt32(EmitContext& ctx, IR::Inst* inst) {
EmitTwoOpVectorOperation<32, DefaultIndexer>(code, ctx, inst, [this](const Xbyak::Xmm& result, const Xbyak::Xmm& operand) {
code.sqrtps(result, operand);
});
}
void EmitX64::EmitFPVectorSqrt64(EmitContext& ctx, IR::Inst* inst) {
EmitTwoOpVectorOperation<64, DefaultIndexer>(code, ctx, inst, [this](const Xbyak::Xmm& result, const Xbyak::Xmm& operand) {
code.sqrtpd(result, operand);
});
}
void EmitX64::EmitFPVectorSub32(EmitContext& ctx, IR::Inst* inst) {
EmitThreeOpVectorOperation<32, DefaultIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::subps);
}

11
src/frontend/ir/ir_emitter.cpp
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@ -2243,6 +2243,17 @@ U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128&
return {};
}
U128 IREmitter::FPVectorSqrt(size_t esize, const U128& a) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorSqrt32, a);
case 64:
return Inst<U128>(Opcode::FPVectorSqrt64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:

1
src/frontend/ir/ir_emitter.h
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@ -344,6 +344,7 @@ public:
U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorSqrt(size_t esize, const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b);
U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);

2
src/frontend/ir/microinstruction.cpp
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@ -333,6 +333,8 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorRSqrtEstimate64:
case Opcode::FPVectorRSqrtStepFused32:
case Opcode::FPVectorRSqrtStepFused64:
case Opcode::FPVectorSqrt32:
case Opcode::FPVectorSqrt64:
case Opcode::FPVectorSub32:
case Opcode::FPVectorSub64:
return true;

2
src/frontend/ir/opcodes.inc
View file

@ -564,6 +564,8 @@ OPCODE(FPVectorRSqrtEstimate32, U128, U128
OPCODE(FPVectorRSqrtEstimate64, U128, U128 )
OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128 )
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 )
OPCODE(FPVectorSqrt32, U128, U128 )
OPCODE(FPVectorSqrt64, U128, U128 )
OPCODE(FPVectorSub32, U128, U128, U128 )
OPCODE(FPVectorSub64, U128, U128, U128 )
OPCODE(FPVectorToSignedFixed32, U128, U128, U8, U8 )