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frontend/ir_emitter: Add half-precision opcode for FPVectorRecipStepFused

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Lioncash 2019-04-13 18:54:53 -04:00 committed by MerryMage
parent 6da0411111
commit 5d5c9f149f
4 changed files with 34 additions and 24 deletions
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6
src/backend/x64/emit_x64_vector_floating_point.cpp
View file

@ -1110,6 +1110,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
} }
}; };
if constexpr (fsize != 16) {
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) { if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@ -1141,10 +1142,15 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
return; return;
} }
}
EmitThreeOpFallback(code, ctx, inst, fallback_fn); EmitThreeOpFallback(code, ctx, inst, fallback_fn);
} }
void EmitX64::EmitFPVectorRecipStepFused16(EmitContext& ctx, IR::Inst* inst) {
EmitRecipStepFused<16>(code, ctx, inst);
}
void EmitX64::EmitFPVectorRecipStepFused32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorRecipStepFused32(EmitContext& ctx, IR::Inst* inst) {
EmitRecipStepFused<32>(code, ctx, inst); EmitRecipStepFused<32>(code, ctx, inst);
} }

2
src/frontend/ir/ir_emitter.cpp
View file

@ -2277,6 +2277,8 @@ U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b) { U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b) {
switch (esize) { switch (esize) {
case 16:
return Inst<U128>(Opcode::FPVectorRecipStepFused16, a, b);
case 32: case 32:
return Inst<U128>(Opcode::FPVectorRecipStepFused32, a, b); return Inst<U128>(Opcode::FPVectorRecipStepFused32, a, b);
case 64: case 64:

1
src/frontend/ir/microinstruction.cpp
View file

@ -338,6 +338,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPVectorPairedAdd64: case Opcode::FPVectorPairedAdd64:
case Opcode::FPVectorRecipEstimate32: case Opcode::FPVectorRecipEstimate32:
case Opcode::FPVectorRecipEstimate64: case Opcode::FPVectorRecipEstimate64:
case Opcode::FPVectorRecipStepFused16:
case Opcode::FPVectorRecipStepFused32: case Opcode::FPVectorRecipStepFused32:
case Opcode::FPVectorRecipStepFused64: case Opcode::FPVectorRecipStepFused64:
case Opcode::FPVectorRoundInt16: case Opcode::FPVectorRoundInt16:

1
src/frontend/ir/opcodes.inc
View file

@ -573,6 +573,7 @@ OPCODE(FPVectorPairedAddLower32, U128, U128
OPCODE(FPVectorPairedAddLower64, U128, U128, U128 ) OPCODE(FPVectorPairedAddLower64, U128, U128, U128 )
OPCODE(FPVectorRecipEstimate32, U128, U128 ) OPCODE(FPVectorRecipEstimate32, U128, U128 )
OPCODE(FPVectorRecipEstimate64, U128, U128 ) OPCODE(FPVectorRecipEstimate64, U128, U128 )
OPCODE(FPVectorRecipStepFused16, U128, U128, U128 )
OPCODE(FPVectorRecipStepFused32, U128, U128, U128 ) OPCODE(FPVectorRecipStepFused32, U128, U128, U128 )
OPCODE(FPVectorRecipStepFused64, U128, U128, U128 ) OPCODE(FPVectorRecipStepFused64, U128, U128, U128 )
OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 )