frontend/ir_emitter: Add half-precision opcode for FPVectorRecipStepFused
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6da0411111
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5d5c9f149f
4 changed files with 34 additions and 24 deletions
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@ -1110,6 +1110,7 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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}
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};
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if constexpr (fsize != 16) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -1141,10 +1142,15 @@ static void EmitRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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}
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EmitThreeOpFallback(code, ctx, inst, fallback_fn);
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}
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void EmitX64::EmitFPVectorRecipStepFused16(EmitContext& ctx, IR::Inst* inst) {
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EmitRecipStepFused<16>(code, ctx, inst);
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}
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void EmitX64::EmitFPVectorRecipStepFused32(EmitContext& ctx, IR::Inst* inst) {
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EmitRecipStepFused<32>(code, ctx, inst);
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}
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@ -2277,6 +2277,8 @@ U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
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U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b) {
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switch (esize) {
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case 16:
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return Inst<U128>(Opcode::FPVectorRecipStepFused16, a, b);
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case 32:
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return Inst<U128>(Opcode::FPVectorRecipStepFused32, a, b);
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case 64:
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@ -338,6 +338,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
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case Opcode::FPVectorPairedAdd64:
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case Opcode::FPVectorRecipEstimate32:
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case Opcode::FPVectorRecipEstimate64:
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case Opcode::FPVectorRecipStepFused16:
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case Opcode::FPVectorRecipStepFused32:
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case Opcode::FPVectorRecipStepFused64:
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case Opcode::FPVectorRoundInt16:
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@ -573,6 +573,7 @@ OPCODE(FPVectorPairedAddLower32, U128, U128
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OPCODE(FPVectorPairedAddLower64, U128, U128, U128 )
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OPCODE(FPVectorRecipEstimate32, U128, U128 )
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OPCODE(FPVectorRecipEstimate64, U128, U128 )
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OPCODE(FPVectorRecipStepFused16, U128, U128, U128 )
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OPCODE(FPVectorRecipStepFused32, U128, U128, U128 )
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OPCODE(FPVectorRecipStepFused64, U128, U128, U128 )
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OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 )
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