A64: Enable half-precision floating point variants of FP data-processing three register instructions
This handles half-precision floating point for: - FMADD - FMSUB - FNMADD - FNMSUB
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1 changed files with 20 additions and 20 deletions
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@ -12,56 +12,56 @@ namespace Dynarmic::A64 {
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bool TranslatorVisitor::FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
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const auto datasize = FPGetDataSize(type);
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if (!datasize || *datasize == 16) {
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if (!datasize) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U32U64 result = ir.FPMulAdd(operanda, operand1, operand2, true);
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const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U16U32U64 result = ir.FPMulAdd(operanda, operand1, operand2, true);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
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const auto datasize = FPGetDataSize(type);
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if (!datasize || *datasize == 16) {
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if (!datasize) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2, true);
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const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U16U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2, true);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
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const auto datasize = FPGetDataSize(type);
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if (!datasize || *datasize == 16) {
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if (!datasize) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2, true);
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const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2, true);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
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const auto datasize = FPGetDataSize(type);
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if (!datasize || *datasize == 16) {
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if (!datasize) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), operand1, operand2, true);
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const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), operand1, operand2, true);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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