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A64: Enable half-precision floating point variants of FP data-processing three register instructions

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This handles half-precision floating point for:

- FMADD
- FMSUB
- FNMADD
- FNMSUB
This commit is contained in:
Lioncash 2019-04-13 00:18:20 -04:00 • committed by MerryMage
parent bd82513199
commit 5f74d25bf7
1 changed files with 20 additions and 20 deletions
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40
src/frontend/A64/translate/impl/floating_point_data_processing_three_register.cpp
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@ -12,56 +12,56 @@ namespace Dynarmic::A64 {
bool TranslatorVisitor::FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) { bool TranslatorVisitor::FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
const auto datasize = FPGetDataSize(type); const auto datasize = FPGetDataSize(type);
if (!datasize || *datasize == 16) { if (!datasize) {
return UnallocatedEncoding(); return UnallocatedEncoding();
} }
const IR::U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
const IR::U32U64 operand2 = V_scalar(*datasize, Vm); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
const IR::U32U64 result = ir.FPMulAdd(operanda, operand1, operand2, true); const IR::U16U32U64 result = ir.FPMulAdd(operanda, operand1, operand2, true);
V_scalar(*datasize, Vd, result); V_scalar(*datasize, Vd, result);
return true; return true;
} }
bool TranslatorVisitor::FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) { bool TranslatorVisitor::FMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
const auto datasize = FPGetDataSize(type); const auto datasize = FPGetDataSize(type);
if (!datasize || *datasize == 16) { if (!datasize) {
return UnallocatedEncoding(); return UnallocatedEncoding();
} }
const IR::U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
const IR::U32U64 operand2 = V_scalar(*datasize, Vm); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
const IR::U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2, true); const IR::U16U32U64 result = ir.FPMulAdd(operanda, ir.FPNeg(operand1), operand2, true);
V_scalar(*datasize, Vd, result); V_scalar(*datasize, Vd, result);
return true; return true;
} }
bool TranslatorVisitor::FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) { bool TranslatorVisitor::FNMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
const auto datasize = FPGetDataSize(type); const auto datasize = FPGetDataSize(type);
if (!datasize || *datasize == 16) { if (!datasize) {
return UnallocatedEncoding(); return UnallocatedEncoding();
} }
const IR::U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
const IR::U32U64 operand2 = V_scalar(*datasize, Vm); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
const IR::U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2, true); const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), ir.FPNeg(operand1), operand2, true);
V_scalar(*datasize, Vd, result); V_scalar(*datasize, Vd, result);
return true; return true;
} }
bool TranslatorVisitor::FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) { bool TranslatorVisitor::FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
const auto datasize = FPGetDataSize(type); const auto datasize = FPGetDataSize(type);
if (!datasize || *datasize == 16) { if (!datasize) {
return UnallocatedEncoding(); return UnallocatedEncoding();
} }
const IR::U32U64 operanda = V_scalar(*datasize, Va); const IR::U16U32U64 operanda = V_scalar(*datasize, Va);
const IR::U32U64 operand1 = V_scalar(*datasize, Vn); const IR::U16U32U64 operand1 = V_scalar(*datasize, Vn);
const IR::U32U64 operand2 = V_scalar(*datasize, Vm); const IR::U16U32U64 operand2 = V_scalar(*datasize, Vm);
const IR::U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), operand1, operand2, true); const IR::U16U32U64 result = ir.FPMulAdd(ir.FPNeg(operanda), operand1, operand2, true);
V_scalar(*datasize, Vd, result); V_scalar(*datasize, Vd, result);
return true; return true;
} }