{a32,a64}_jitstate: Remove FPSCR_UFC
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parent
366d63f4b4
commit
622c02f537
6 changed files with 0 additions and 10 deletions
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@ -271,7 +271,6 @@ void TransferJitState(A32JitState& dest, const A32JitState& src, bool reset_rsb)
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dest.ExtReg = src.ExtReg;
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dest.ExtReg = src.ExtReg;
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dest.guest_MXCSR = src.guest_MXCSR;
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dest.guest_MXCSR = src.guest_MXCSR;
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dest.FPSCR_IDC = src.FPSCR_IDC;
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dest.FPSCR_IDC = src.FPSCR_IDC;
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dest.FPSCR_UFC = src.FPSCR_UFC;
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dest.FPSCR_mode = src.FPSCR_mode;
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dest.FPSCR_mode = src.FPSCR_mode;
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dest.FPSCR_nzcv = src.FPSCR_nzcv;
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dest.FPSCR_nzcv = src.FPSCR_nzcv;
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if (reset_rsb) {
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if (reset_rsb) {
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@ -157,13 +157,11 @@ u32 A32JitState::Fpscr() const {
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ASSERT((FPSCR_mode & ~FPSCR_MODE_MASK) == 0);
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ASSERT((FPSCR_mode & ~FPSCR_MODE_MASK) == 0);
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ASSERT((FPSCR_nzcv & ~FPSCR_NZCV_MASK) == 0);
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ASSERT((FPSCR_nzcv & ~FPSCR_NZCV_MASK) == 0);
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ASSERT((FPSCR_IDC & ~(1 << 7)) == 0);
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ASSERT((FPSCR_IDC & ~(1 << 7)) == 0);
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ASSERT((FPSCR_UFC & ~(1 << 3)) == 0);
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u32 FPSCR = FPSCR_mode | FPSCR_nzcv;
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u32 FPSCR = FPSCR_mode | FPSCR_nzcv;
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FPSCR |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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FPSCR |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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FPSCR |= FPSCR_IDC;
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FPSCR |= FPSCR_IDC;
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FPSCR |= FPSCR_UFC;
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FPSCR |= fpsr_exc;
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FPSCR |= fpsr_exc;
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return FPSCR;
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return FPSCR;
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@ -184,7 +182,6 @@ void A32JitState::SetFpscr(u32 FPSCR) {
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// Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC
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// Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC
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FPSCR_IDC = 0;
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FPSCR_IDC = 0;
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FPSCR_UFC = 0;
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fpsr_exc = FPSCR & 0x9F;
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fpsr_exc = FPSCR & 0x9F;
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if (Common::Bit<24>(FPSCR)) {
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if (Common::Bit<24>(FPSCR)) {
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@ -70,7 +70,6 @@ struct A32JitState {
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u32 fpsr_exc = 0;
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u32 fpsr_exc = 0;
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u32 fpsr_qc = 0; // Dummy value
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u32 fpsr_qc = 0; // Dummy value
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u32 FPSCR_IDC = 0;
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u32 FPSCR_IDC = 0;
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u32 FPSCR_UFC = 0;
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u32 FPSCR_mode = 0;
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u32 FPSCR_mode = 0;
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u32 FPSCR_nzcv = 0;
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u32 FPSCR_nzcv = 0;
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u32 old_FPSCR = 0;
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u32 old_FPSCR = 0;
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@ -104,7 +104,6 @@ u32 A64JitState::GetFpsr() const {
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fpsr |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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fpsr |= (guest_MXCSR & 0b0000000000001); // IOC = IE
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fpsr |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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fpsr |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
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fpsr |= FPSCR_IDC;
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fpsr |= FPSCR_IDC;
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fpsr |= FPSCR_UFC;
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fpsr |= fpsr_exc;
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fpsr |= fpsr_exc;
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fpsr |= (fpsr_qc == 0 ? 0 : 1) << 27;
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fpsr |= (fpsr_qc == 0 ? 0 : 1) << 27;
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return fpsr;
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return fpsr;
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@ -113,7 +112,6 @@ u32 A64JitState::GetFpsr() const {
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void A64JitState::SetFpsr(u32 value) {
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void A64JitState::SetFpsr(u32 value) {
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guest_MXCSR &= ~0x0000003D;
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guest_MXCSR &= ~0x0000003D;
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FPSCR_IDC = 0;
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FPSCR_IDC = 0;
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FPSCR_UFC = 0;
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fpsr_qc = (value >> 27) & 1;
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fpsr_qc = (value >> 27) & 1;
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fpsr_exc = value & 0x9F;
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fpsr_exc = value & 0x9F;
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}
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}
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@ -74,7 +74,6 @@ struct A64JitState {
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u32 fpsr_exc = 0;
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u32 fpsr_exc = 0;
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u32 fpsr_qc = 0;
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u32 fpsr_qc = 0;
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u32 FPSCR_IDC = 0;
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u32 FPSCR_IDC = 0;
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u32 FPSCR_UFC = 0;
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u32 fpcr = 0;
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u32 fpcr = 0;
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u32 GetFpcr() const;
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u32 GetFpcr() const;
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u32 GetFpsr() const;
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u32 GetFpsr() const;
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@ -25,7 +25,6 @@ struct JitStateInfo {
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, offsetof_rsb_codeptrs(offsetof(JitStateType, rsb_codeptrs))
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, offsetof_rsb_codeptrs(offsetof(JitStateType, rsb_codeptrs))
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, offsetof_CPSR_nzcv(offsetof(JitStateType, CPSR_nzcv))
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, offsetof_CPSR_nzcv(offsetof(JitStateType, CPSR_nzcv))
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, offsetof_FPSCR_IDC(offsetof(JitStateType, FPSCR_IDC))
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, offsetof_FPSCR_IDC(offsetof(JitStateType, FPSCR_IDC))
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, offsetof_FPSCR_UFC(offsetof(JitStateType, FPSCR_UFC))
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, offsetof_fpsr_exc(offsetof(JitStateType, fpsr_exc))
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, offsetof_fpsr_exc(offsetof(JitStateType, fpsr_exc))
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, offsetof_fpsr_qc(offsetof(JitStateType, fpsr_qc))
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, offsetof_fpsr_qc(offsetof(JitStateType, fpsr_qc))
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{}
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{}
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@ -40,7 +39,6 @@ struct JitStateInfo {
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const size_t offsetof_rsb_codeptrs;
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const size_t offsetof_rsb_codeptrs;
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const size_t offsetof_CPSR_nzcv;
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const size_t offsetof_CPSR_nzcv;
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const size_t offsetof_FPSCR_IDC;
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const size_t offsetof_FPSCR_IDC;
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const size_t offsetof_FPSCR_UFC;
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const size_t offsetof_fpsr_exc;
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const size_t offsetof_fpsr_exc;
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const size_t offsetof_fpsr_qc;
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const size_t offsetof_fpsr_qc;
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};
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};
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