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A64: Handle half-precision variants of FP->Fixed-point instructions

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Lioncash 2019-04-15 00:57:34 -04:00 committed by MerryMage
parent 427b7afd66
commit 64e3d233f4
2 changed files with 8 additions and 10 deletions
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8
src/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
View file

@ -69,7 +69,7 @@ bool TranslatorVisitor::UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) {
const size_t intsize = sf ? 64 : 32;
const auto fltsize = FPGetDataSize(type);
if (!fltsize || *fltsize == 16) {
if (!fltsize) {
return UnallocatedEncoding();
}
if (!sf && !scale.Bit<5>()) {
@ -77,7 +77,7 @@ bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
}
const u8 fracbits = 64 - scale.ZeroExtend<u8>();
const IR::U32U64 fltval = V_scalar(*fltsize, Vn);
const IR::U16U32U64 fltval = V_scalar(*fltsize, Vn);
IR::U32U64 intval;
if (intsize == 32) {
intval = ir.FPToFixedS32(fltval, fracbits, FP::RoundingMode::TowardsZero);
@ -94,7 +94,7 @@ bool TranslatorVisitor::FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) {
const size_t intsize = sf ? 64 : 32;
const auto fltsize = FPGetDataSize(type);
if (!fltsize || *fltsize == 16) {
if (!fltsize) {
return UnallocatedEncoding();
}
if (!sf && !scale.Bit<5>()) {
@ -102,7 +102,7 @@ bool TranslatorVisitor::FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec
}
const u8 fracbits = 64 - scale.ZeroExtend<u8>();
const IR::U32U64 fltval = V_scalar(*fltsize, Vn);
const IR::U16U32U64 fltval = V_scalar(*fltsize, Vn);
IR::U32U64 intval;
if (intsize == 32) {
intval = ir.FPToFixedU32(fltval, fracbits, FP::RoundingMode::TowardsZero);

10
src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
View file

@ -119,11 +119,11 @@ bool TranslatorVisitor::FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm
static bool FloaingPointConvertSignedInteger(TranslatorVisitor& v, bool sf, Imm<2> type, Vec Vn, Reg Rd, FP::RoundingMode rounding_mode) {
const size_t intsize = sf ? 64 : 32;
const auto fltsize = FPGetDataSize(type);
if (!fltsize || *fltsize == 16) {
if (!fltsize) {
return v.UnallocatedEncoding();
}
const IR::U32U64 fltval = v.V_scalar(*fltsize, Vn);
const IR::U16U32U64 fltval = v.V_scalar(*fltsize, Vn);
IR::U32U64 intval;
if (intsize == 32) {
@ -135,18 +135,17 @@ static bool FloaingPointConvertSignedInteger(TranslatorVisitor& v, bool sf, Imm<
}
v.X(intsize, Rd, intval);
return true;
}
static bool FloaingPointConvertUnsignedInteger(TranslatorVisitor& v, bool sf, Imm<2> type, Vec Vn, Reg Rd, FP::RoundingMode rounding_mode) {
const size_t intsize = sf ? 64 : 32;
const auto fltsize = FPGetDataSize(type);
if (!fltsize || *fltsize == 16) {
if (!fltsize) {
return v.UnallocatedEncoding();
}
const IR::U32U64 fltval = v.V_scalar(*fltsize, Vn);
const IR::U16U32U64 fltval = v.V_scalar(*fltsize, Vn);
IR::U32U64 intval;
if (intsize == 32) {
@ -158,7 +157,6 @@ static bool FloaingPointConvertUnsignedInteger(TranslatorVisitor& v, bool sf, Im
}
v.X(intsize, Rd, intval);
return true;
}