General: Convert multiple namespace specifiers to nested namespace specifiers where applicable

Makes namespacing a little less noisy

src/backend_x64/a32_emit_x64.cpp

@@ -28,8 +28,7 @@
 // TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
 // TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -1212,5 +1211,4 @@ void A32EmitX64::EmitPatchMovRcx(CodePtr target_code_ptr) {
     code->EnsurePatchLocationSize(patch_location, 10);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a32_emit_x64.h

@@ -16,8 +16,7 @@
 #include "frontend/A32/location_descriptor.h"
 #include "frontend/ir/terminal.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class RegAlloc;
 
@@ -84,5 +83,4 @@ protected:
     void EmitPatchMovRcx(CodePtr target_code_ptr = nullptr) override;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a32_interface.cpp

@@ -29,8 +29,7 @@
 #include "frontend/ir/location_descriptor.h"
 #include "ir_opt/passes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 using namespace BackendX64;
 
@@ -325,5 +324,4 @@ std::string Jit::Disassemble(const IR::LocationDescriptor& descriptor) {
     return impl->Disassemble(descriptor);
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/backend_x64/a32_jitstate.cpp

@@ -11,8 +11,7 @@
 #include "common/common_types.h"
 #include "frontend/A32/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 /**
  * CPSR Bits
@@ -203,5 +202,4 @@ u64 A32JitState::GetUniqueHash() const {
     return CPSR_et | FPSCR_mode | (static_cast<u64>(Reg[15]) << 32);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a32_jitstate.h

@@ -12,8 +12,7 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class BlockOfCode;
 
@@ -84,5 +83,4 @@ struct A32JitState {
 
 using CodePtr = const void*;
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a64_emit_x64.cpp

@@ -27,8 +27,7 @@
 // TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
 // TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -534,5 +533,4 @@ void A64EmitX64::EmitPatchMovRcx(CodePtr target_code_ptr) {
     code->EnsurePatchLocationSize(patch_location, 10);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a64_emit_x64.h

@@ -13,8 +13,7 @@
 #include "frontend/A64/location_descriptor.h"
 #include "frontend/ir/terminal.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class RegAlloc;
 
@@ -70,5 +69,4 @@ protected:
     void EmitPatchMovRcx(CodePtr target_code_ptr = nullptr) override;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a64_interface.cpp

@@ -21,8 +21,7 @@
 #include "frontend/ir/basic_block.h"
 #include "ir_opt/passes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 using namespace BackendX64;
 
@@ -311,5 +310,4 @@ bool Jit::IsExecuting() const {
     return impl->IsExecuting();
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/backend_x64/a64_jitstate.cpp

@@ -7,8 +7,7 @@
 #include "backend_x64/a64_jitstate.h"
 #include "frontend/A64/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 u64 A64JitState::GetUniqueHash() const {
     u64 fpcr_u64 = static_cast<u64>(fpcr & A64::LocationDescriptor::FPCR_MASK) << 37;
@@ -16,5 +15,4 @@ u64 A64JitState::GetUniqueHash() const {
     return pc_u64 | fpcr_u64;
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/a64_jitstate.h

@@ -12,8 +12,7 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class BlockOfCode;
 
@@ -82,5 +81,4 @@ struct A64JitState {
 
 using CodePtr = const void*;
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/abi.cpp

@@ -20,8 +20,7 @@
 #include "common/common_types.h"
 #include "common/iterator_util.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 constexpr size_t GPR_SIZE = 8;
 constexpr size_t XMM_SIZE = 16;
@@ -127,5 +126,4 @@ void ABI_PopCallerSaveRegistersAndAdjustStack(Xbyak::CodeGenerator* code, size_t
     ABI_PopRegistersAndAdjustStack(code, frame_size, ABI_ALL_CALLER_SAVE);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/abi.h

@@ -9,8 +9,7 @@
 
 #include "backend_x64/hostloc.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 #ifdef _WIN32
 
@@ -115,5 +114,4 @@ void ABI_PopCalleeSaveRegistersAndAdjustStack(Xbyak::CodeGenerator* code, size_t
 void ABI_PushCallerSaveRegistersAndAdjustStack(Xbyak::CodeGenerator* code, size_t frame_size = 0);
 void ABI_PopCallerSaveRegistersAndAdjustStack(Xbyak::CodeGenerator* code, size_t frame_size = 0);
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/block_of_code.cpp

@@ -14,8 +14,7 @@
 #include "backend_x64/block_of_code.h"
 #include "common/assert.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 #ifdef _WIN32
 const Xbyak::Reg64 BlockOfCode::ABI_RETURN = Xbyak::util::rax;
@@ -243,5 +242,4 @@ bool BlockOfCode::DoesCpuSupport(Xbyak::util::Cpu::Type type) const {
 #endif
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/block_of_code.h

@@ -18,8 +18,7 @@
 #include "common/common_types.h"
 #include "dynarmic/A32/callbacks.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using CodePtr = const void*;
 
@@ -147,5 +146,4 @@ private:
     Xbyak::util::Cpu cpu_info;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/block_range_information.cpp

@@ -12,8 +12,7 @@
 #include "backend_x64/block_range_information.h"
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 template <typename ProgramCounterType>
 void BlockRangeInformation<ProgramCounterType>::AddRange(boost::icl::discrete_interval<ProgramCounterType> range, IR::LocationDescriptor location) {
@@ -43,5 +42,4 @@ std::unordered_set<IR::LocationDescriptor> BlockRangeInformation<ProgramCounterT
 template class BlockRangeInformation<u32>;
 template class BlockRangeInformation<u64>;
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/block_range_information.h

@@ -13,8 +13,7 @@
 
 #include "frontend/ir/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 template <typename ProgramCounterType>
 class BlockRangeInformation {
@@ -27,5 +26,4 @@ private:
     boost::icl::interval_map<ProgramCounterType, std::set<IR::LocationDescriptor>> block_ranges;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/callback.cpp

@@ -7,8 +7,7 @@
 #include "backend_x64/block_of_code.h"
 #include "backend_x64/callback.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 void SimpleCallback::EmitCall(BlockOfCode* code, std::function<void()> l) {
     l();
@@ -54,5 +53,4 @@ void ArgCallback::EmitCall(BlockOfCode* code, std::function<void(Xbyak::Reg64, X
     code->CallFunction(fn);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/callback.h

@@ -12,8 +12,7 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class BlockOfCode;
 
@@ -60,5 +59,4 @@ private:
     u64 arg;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/constant_pool.cpp

@@ -10,8 +10,7 @@
 #include "backend_x64/constant_pool.h"
 #include "common/assert.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 ConstantPool::ConstantPool(BlockOfCode* code, size_t size) : code(code), pool_size(size) {
     code->int3();
@@ -32,5 +31,4 @@ Xbyak::Address ConstantPool::GetConstant(u64 constant) {
     return code->xword[code->rip + iter->second];
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/constant_pool.h

@@ -12,8 +12,7 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class BlockOfCode;
 
@@ -38,5 +37,4 @@ private:
     u8* current_pool_ptr;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64.cpp

@@ -18,8 +18,7 @@
 // TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
 // TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -318,5 +317,4 @@ void EmitX64::InvalidateBasicBlocks(const std::unordered_set<IR::LocationDescrip
     }
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64.h

@@ -19,14 +19,12 @@
 #include "frontend/ir/location_descriptor.h"
 #include "frontend/ir/terminal.h"
 
-namespace Dynarmic {
+namespace Dynarmic::IR {
-
-namespace IR {
 class Block;
 class Inst;
-} // namespace IR
+} // namespace Dynarmic::IR
 
-namespace BackendX64 {
+namespace Dynarmic::BackendX64 {
 
 class BlockOfCode;
 
@@ -107,5 +105,4 @@ protected:
     std::unordered_map<IR::LocationDescriptor, PatchInformation> patch_information;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64_data_processing.cpp

@@ -12,8 +12,7 @@
 #include "frontend/ir/microinstruction.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -1255,5 +1254,4 @@ void EmitX64::EmitCountLeadingZeros64(EmitContext& ctx, IR::Inst* inst) {
    }
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64_floating_point.cpp

@@ -12,8 +12,7 @@
 #include "frontend/ir/microinstruction.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -600,5 +599,4 @@ void EmitX64::EmitFPU32ToDouble(EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.DefineValue(inst, to);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64_packed.cpp

@@ -12,8 +12,7 @@
 #include "frontend/ir/microinstruction.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -702,5 +701,4 @@ void EmitX64::EmitPackedSelect(EmitContext& ctx, IR::Inst* inst) {
     }
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64_saturation.cpp

@@ -13,8 +13,7 @@
 #include "frontend/ir/microinstruction.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -149,5 +148,4 @@ void EmitX64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.DefineValue(inst, result);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/emit_x64_vector.cpp

@@ -12,8 +12,7 @@
 #include "frontend/ir/microinstruction.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 using namespace Xbyak::util;
 
@@ -457,5 +456,4 @@ void EmitX64::EmitVectorZeroUpper(EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.DefineValue(inst, a);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/exception_handler_generic.cpp

@@ -6,8 +6,7 @@
 
 #include "backend_x64/block_of_code.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 struct BlockOfCode::ExceptionHandler::Impl final {
 };
@@ -19,5 +18,4 @@ void BlockOfCode::ExceptionHandler::Register(BlockOfCode*) {
     // Do nothing
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/hostloc.cpp

@@ -8,8 +8,7 @@
 
 #include "backend_x64/hostloc.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 Xbyak::Reg64 HostLocToReg64(HostLoc loc) {
     ASSERT(HostLocIsGPR(loc));
@@ -21,5 +20,4 @@ Xbyak::Xmm HostLocToXmm(HostLoc loc) {
     return Xbyak::Xmm(static_cast<int>(loc) - static_cast<int>(HostLoc::XMM0));
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/hostloc.h

@@ -10,8 +10,7 @@
 #include "common/assert.h"
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 enum class HostLoc {
     // Ordering of the registers is intentional. See also: HostLocToX64.
@@ -113,5 +112,4 @@ Xbyak::Address SpillToOpArg(HostLoc loc) {
     return JitStateType::GetSpillLocationFromIndex(i);
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/jitstate_info.h

@@ -10,8 +10,7 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 struct JitStateInfo {
     template <typename JitStateType>
@@ -44,5 +43,4 @@ struct JitStateInfo {
     const size_t offsetof_FPSCR_UFC;
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/oparg.h

@@ -10,8 +10,7 @@
 
 #include "common/assert.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 struct OpArg {
     OpArg() : type(Type::Operand), inner_operand() {}
@@ -76,5 +75,4 @@ private:
     };
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/reg_alloc.cpp

@@ -14,8 +14,7 @@
 #include "backend_x64/reg_alloc.h"
 #include "common/assert.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 static u64 ImmediateToU64(const IR::Value& imm) {
     switch (imm.GetType()) {
@@ -641,5 +640,4 @@ void RegAlloc::EmitExchange(HostLoc a, HostLoc b) {
     }
 }
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/backend_x64/reg_alloc.h

@@ -21,8 +21,7 @@
 #include "frontend/ir/microinstruction.h"
 #include "frontend/ir/value.h"
 
-namespace Dynarmic {
+namespace Dynarmic::BackendX64 {
-namespace BackendX64 {
 
 class RegAlloc;
 
@@ -150,5 +149,4 @@ private:
     void EmitExchange(HostLoc a, HostLoc b);
 };
 
-} // namespace BackendX64
+} // namespace Dynarmic::BackendX64
-} // namespace Dynarmic

src/common/address_range.h

@@ -8,8 +8,7 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
 
 struct AddressRange {
     u32 start_address;
@@ -21,5 +20,4 @@ struct AddressRange {
     }
 };
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/common/bit_util.h

@@ -13,8 +13,7 @@
 
 #include "common/assert.h"
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
 
 /// The size of a type in terms of bits
 template<typename T>
@@ -135,5 +134,4 @@ inline T RotateRight(T value, size_t amount) {
     return static_cast<T>((x >> amount) | (x << (BitSize<T>() - amount)));
 }
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/common/intrusive_list.h

@@ -13,8 +13,7 @@
 
 #include "common/assert.h"
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
 
 template <typename T> class IntrusiveList;
 template <typename T> class IntrusiveListIterator;
@@ -374,5 +373,4 @@ void swap(IntrusiveList<T>& lhs, IntrusiveList<T>& rhs) noexcept {
     lhs.swap(rhs);
 }
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/common/iterator_util.h

@@ -8,9 +8,7 @@
 
 #include <iterator>
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
-
 namespace detail {
 
 template<typename T>
@@ -35,5 +33,4 @@ detail::ReverseAdapter<T> Reverse(T&& iterable) {
     return detail::ReverseAdapter<T>{iterable};
 }
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/common/memory_pool.cpp

@@ -8,8 +8,7 @@
 
 #include "common/memory_pool.h"
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
 
 Pool::Pool(size_t object_size, size_t initial_pool_size) : object_size(object_size), slab_size(initial_pool_size) {
     AllocateNewSlab();
@@ -42,6 +41,4 @@ void Pool::AllocateNewSlab() {
     remaining = slab_size;
 }
 
-
+} // namespace Dynarmic::Common
-} // namespace Common
-} // namespace Dynarmic

src/common/memory_pool.h

@@ -9,8 +9,7 @@
 #include <cstddef>
 #include <vector>
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
 
 class Pool {
 public:
@@ -44,5 +43,4 @@ private:
     std::vector<char*> slabs;
 };
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/common/mp.h

@@ -9,8 +9,7 @@
 #include <cstddef>
 #include <tuple>
 
-namespace Dynarmic {
+namespace Dynarmic::mp {
-namespace mp {
 
 /// Used to provide information about an arbitrary function.
 template <typename Function>
@@ -80,5 +79,4 @@ using return_type_t = typename FunctionInfo<Function>::return_type;
 template <typename Function>
 using class_type_t = typename FunctionInfo<Function>::class_type;
 
-} // namespace mp
+} // namespace Dynarmic::mp
-} // namespace Dynarmic

src/common/string_util.h

@@ -6,13 +6,11 @@
 
 #pragma once
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
 
 template <typename T>
 constexpr char SignToChar(T value) {
     return value >= 0 ? '+' : '-';
 }
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/common/variant_util.h

@@ -8,9 +8,7 @@
 
 #include <boost/variant.hpp>
 
-namespace Dynarmic {
+namespace Dynarmic::Common {
-namespace Common {
-
 namespace detail {
 
 template <typename ReturnT, typename Lambda>
@@ -29,5 +27,4 @@ inline ReturnT VisitVariant(Variant&& variant, Lambda&& lambda) {
     return boost::apply_visitor(detail::VariantVisitor<ReturnT, Lambda>(std::move(lambda)), variant);
 }
 
-} // namespace Common
+} // namespace Dynarmic::Common
-} // namespace Dynarmic

src/frontend/A32/FPSCR.h

@@ -11,8 +11,7 @@
 #include "common/bit_util.h"
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 /**
  * Representation of the Floating-Point Status and Control Register.
@@ -195,5 +194,4 @@ inline bool operator!=(FPSCR lhs, FPSCR rhs) {
     return !operator==(lhs, rhs);
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/PSR.h

@@ -9,8 +9,7 @@
 #include "common/bit_util.h"
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 /**
  * Program Status Register
@@ -221,5 +220,4 @@ inline bool operator!=(PSR lhs, PSR rhs) {
     return !operator==(lhs, rhs);
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/decoder/arm.h

@@ -19,8 +19,7 @@
 #include "frontend/decoder/decoder_detail.h"
 #include "frontend/decoder/matcher.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 template <typename Visitor>
 using ArmMatcher = Decoder::Matcher<Visitor, u32>;
@@ -330,5 +329,4 @@ boost::optional<const ArmMatcher<V>&> DecodeArm(u32 instruction) {
     return iter != table.end() ? boost::optional<const ArmMatcher<V>&>(*iter) : boost::none;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/decoder/thumb16.h

@@ -14,8 +14,7 @@
 #include "frontend/decoder/decoder_detail.h"
 #include "frontend/decoder/matcher.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 template <typename Visitor>
 using Thumb16Matcher = Decoder::Matcher<Visitor, u16>;
@@ -123,5 +122,4 @@ boost::optional<const Thumb16Matcher<V>&> DecodeThumb16(u16 instruction) {
     return iter != table.end() ? boost::optional<const Thumb16Matcher<V>&>(*iter) : boost::none;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/decoder/thumb32.h

@@ -14,8 +14,7 @@
 #include "frontend/decoder/decoder_detail.h"
 #include "frontend/decoder/matcher.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 template <typename Visitor>
 using Thumb32Matcher = Decoder::Matcher<Visitor, u32>;
@@ -43,5 +42,4 @@ boost::optional<const Thumb32Matcher<V>&> DecodeThumb32(u32 instruction) {
     return iter != table.end() ? boost::optional<const Thumb32Matcher<V>&>(*iter) : boost::none;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/decoder/vfp2.h

@@ -14,8 +14,7 @@
 #include "frontend/decoder/decoder_detail.h"
 #include "frontend/decoder/matcher.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 template <typename Visitor>
 using VFP2Matcher = Decoder::Matcher<Visitor, u32>;
@@ -88,5 +87,4 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
     return iter != table.end() ? boost::optional<const VFP2Matcher<V>&>(*iter) : boost::none;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/disassembler/disassembler.h

@@ -10,11 +10,9 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 std::string DisassembleArm(u32 instruction);
 std::string DisassembleThumb16(u16 instruction);
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/disassembler/disassembler_arm.cpp

@@ -17,8 +17,7 @@
 #include "frontend/A32/disassembler/disassembler.h"
 #include "frontend/A32/types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 class DisassemblerVisitor {
 public:
@@ -1079,5 +1078,4 @@ std::string DisassembleArm(u32 instruction) {
     }
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/disassembler/disassembler_thumb.cpp

@@ -16,8 +16,7 @@
 #include "frontend/A32/disassembler/disassembler.h"
 #include "frontend/A32/types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 class DisassemblerVisitor {
 public:
@@ -332,5 +331,4 @@ std::string DisassembleThumb16(u16 instruction) {
     return !decoder ? fmt::format("UNKNOWN: {:x}", instruction) : decoder->call(visitor, instruction);
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/ir_emitter.cpp

@@ -8,8 +8,7 @@
 #include "frontend/A32/ir_emitter.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 using Opcode = IR::Opcode;
 
@@ -320,5 +319,4 @@ void IREmitter::CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer,
     Inst(Opcode::A32CoprocStoreWords, IR::Value(coproc_info), address);
 }
 
-} // namespace IR
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/ir_emitter.h

@@ -16,8 +16,7 @@
 #include "frontend/ir/ir_emitter.h"
 #include "frontend/ir/value.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 /**
  * Convenience class to construct a basic block of the intermediate representation.
@@ -87,5 +86,4 @@ public:
     void CoprocStoreWords(size_t coproc_no, bool two, bool long_transfer, CoprocReg CRd, const IR::U32& address, bool has_option, u8 option);
 };
 
-} // namespace IR
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/location_descriptor.cpp

@@ -8,8 +8,7 @@
 #include <fmt/format.h>
 #include "frontend/A32/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 std::ostream& operator<<(std::ostream& o, const LocationDescriptor& loc) {
     o << fmt::format("{{{},{},{},{}}}",
@@ -20,5 +19,4 @@ std::ostream& operator<<(std::ostream& o, const LocationDescriptor& loc) {
     return o;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/location_descriptor.h

@@ -14,8 +14,7 @@
 #include "frontend/A32/PSR.h"
 #include "frontend/ir/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 /**
  * LocationDescriptor describes the location of a basic block.
@@ -108,8 +107,7 @@ private:
  */
 std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor);
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic
 
 namespace std {
 template <>

src/frontend/A32/translate/translate.cpp

@@ -8,8 +8,7 @@
 #include "frontend/A32/translate/translate.h"
 #include "frontend/ir/basic_block.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 IR::Block TranslateArm(LocationDescriptor descriptor, MemoryReadCodeFuncType memory_read_code);
 IR::Block TranslateThumb(LocationDescriptor descriptor, MemoryReadCodeFuncType memory_read_code);
@@ -18,5 +17,4 @@ IR::Block Translate(LocationDescriptor descriptor, MemoryReadCodeFuncType memory
     return (descriptor.TFlag() ? TranslateThumb : TranslateArm)(descriptor, memory_read_code);
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate.h

@@ -7,13 +7,11 @@
 
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::IR {
-
-namespace IR {
 class Block;
-} // namespace IR
+} // namespace Dynarmic::IR
 
-namespace A32 {
+namespace Dynarmic::A32 {
 
 class LocationDescriptor;
 
@@ -27,5 +25,4 @@ using MemoryReadCodeFuncType = u32 (*)(u32 vaddr);
  */
 IR::Block Translate(LocationDescriptor descriptor, MemoryReadCodeFuncType memory_read_code);
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm.cpp

@@ -15,8 +15,7 @@
 #include "frontend/A32/types.h"
 #include "frontend/ir/basic_block.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 static bool CondCanContinue(ConditionalState cond_state, const A32::IREmitter& ir) {
     ASSERT_MSG(cond_state != ConditionalState::Break, "Should never happen.");
@@ -157,5 +156,4 @@ IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitRegShift(IR::U32 value, Sh
     return {};
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/branch.cpp

@@ -8,8 +8,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_B(Cond cond, Imm24 imm24) {
     u32 imm32 = Common::SignExtend<26, u32>(imm24 << 2) + 8;
@@ -77,5 +76,4 @@ bool ArmTranslatorVisitor::arm_BXJ(Cond cond, Reg m) {
     return arm_BX(cond, m);
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/coprocessor.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_CDP(Cond cond, size_t opc1, CoprocReg CRn, CoprocReg CRd, size_t coproc_no, size_t opc2, CoprocReg CRm) {
     if ((coproc_no & 0b1110) == 0b1010)
@@ -146,5 +145,4 @@ bool ArmTranslatorVisitor::arm_STC(Cond cond, bool p, bool u, bool d, bool w, Re
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/data_processing.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
     // ADC{S}<c> <Rd>, <Rn>, #<imm>
@@ -889,5 +888,4 @@ bool ArmTranslatorVisitor::arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift,
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/exception_generating.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_BKPT(Cond /*cond*/, Imm12 /*imm12*/, Imm4 /*imm4*/) {
     return InterpretThisInstruction();
@@ -30,5 +29,4 @@ bool ArmTranslatorVisitor::arm_UDF() {
     return InterpretThisInstruction();
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/extension.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 static IR::U32 Rotate(A32::IREmitter& ir, Reg m, SignExtendRotation rotate) {
     const u8 rotate_by = static_cast<u8>(static_cast<size_t>(rotate) * 8);
@@ -181,5 +180,4 @@ bool ArmTranslatorVisitor::arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate,
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/load_store.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_LDRBT() {
     ASSERT_MSG(false, "System instructions unimplemented");
@@ -755,5 +754,4 @@ bool ArmTranslatorVisitor::arm_STM_usr() {
     return InterpretThisInstruction();
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/misc.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     if (d == Reg::PC || m == Reg::PC)
@@ -32,5 +31,4 @@ bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/multiply.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 // Multiply (Normal) instructions
 bool ArmTranslatorVisitor::arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) {
@@ -428,5 +427,4 @@ bool ArmTranslatorVisitor::arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) {
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/packing.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) {
     if (n == Reg::PC || d == Reg::PC || m == Reg::PC)
@@ -37,5 +36,4 @@ bool ArmTranslatorVisitor::arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m)
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/parallel.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 // Parallel Add/Subtract (Modulo arithmetic) instructions
 bool ArmTranslatorVisitor::arm_SADD8(Cond cond, Reg n, Reg d, Reg m) {
@@ -365,5 +364,4 @@ bool ArmTranslatorVisitor::arm_UHSUB16(Cond cond, Reg n, Reg d, Reg m) {
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/reversal.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) {
     // REV<c> <Rd>, <Rm>
@@ -47,5 +46,4 @@ bool ArmTranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) {
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/saturated.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) {
     return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result);
@@ -240,5 +239,4 @@ bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/status_register_access.cpp

@@ -8,8 +8,7 @@
 
 #include "common/bit_util.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_CPS() {
     return InterpretThisInstruction();
@@ -76,5 +75,4 @@ bool ArmTranslatorVisitor::arm_SRS() {
     return InterpretThisInstruction();
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/synchronization.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 bool ArmTranslatorVisitor::arm_CLREX() {
     // CLREX
@@ -158,5 +157,4 @@ bool ArmTranslatorVisitor::arm_SWPB(Cond cond, Reg n, Reg t, Reg t2) {
 }
 
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/translate_arm.h

@@ -9,8 +9,7 @@
 #include "frontend/A32/ir_emitter.h"
 #include "frontend/A32/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 enum class ConditionalState {
     /// We haven't met any conditional instructions yet.
@@ -384,5 +383,4 @@ struct ArmTranslatorVisitor final {
     bool vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8);
 };
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_arm/vfp2.cpp

@@ -6,8 +6,7 @@
 
 #include "translate_arm.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 static ExtReg ToExtReg(bool sz, size_t base, bool bit) {
     if (sz) {
@@ -827,5 +826,4 @@ bool ArmTranslatorVisitor::vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool
     return true;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/translate/translate_thumb.cpp

@@ -15,9 +15,7 @@
 #include "frontend/A32/translate/translate.h"
 #include "frontend/A32/types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
-
 namespace {
 
 struct ThumbTranslatorVisitor final {
@@ -915,5 +913,4 @@ IR::Block TranslateThumb(LocationDescriptor descriptor, MemoryReadCodeFuncType m
     return block;
 }
 
-} // namespace A32
+} // namepsace Dynarmic::A32
-} // namepsace Dynarmic

src/frontend/A32/types.cpp

@@ -10,8 +10,7 @@
 #include "common/bit_util.h"
 #include "frontend/A32/types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 const char* CondToString(Cond cond, bool explicit_al) {
     constexpr std::array<const char*, 15> cond_strs = {
@@ -78,5 +77,4 @@ std::ostream& operator<<(std::ostream& o, RegList reg_list) {
     return o;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A32/types.h

@@ -16,8 +16,7 @@
 #include "common/common_types.h"
 #include "frontend/ir/cond.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A32 {
-namespace A32 {
 
 using Cond = IR::Cond;
 
@@ -118,5 +117,4 @@ inline ExtReg operator+(ExtReg reg, size_t number) {
     return new_reg;
 }
 
-} // namespace A32
+} // namespace Dynarmic::A32
-} // namespace Dynarmic

src/frontend/A64/FPCR.h

@@ -11,8 +11,7 @@
 #include "common/bit_util.h"
 #include "common/common_types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 /**
  * Representation of the Floating-Point Control Register.
@@ -108,5 +107,4 @@ inline bool operator!=(FPCR lhs, FPCR rhs) {
     return !operator==(lhs, rhs);
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/decoder/a64.h

@@ -17,8 +17,7 @@
 #include "frontend/decoder/decoder_detail.h"
 #include "frontend/decoder/matcher.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 template <typename Visitor>
 using Matcher = Decoder::Matcher<Visitor, u32>;
@@ -49,5 +48,4 @@ boost::optional<const Matcher<Visitor>&> Decode(u32 instruction) {
     return iter != table.end() ? boost::optional<const Matcher<Visitor>&>(*iter) : boost::none;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/imm.h

@@ -11,8 +11,7 @@
 #include "common/common_types.h"
 #include "common/math_util.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 /**
  * Imm represents an immediate value in an AArch64 instruction.
@@ -96,5 +95,4 @@ auto concatenate(Imm<first_bit_size> first, Imm<rest_bit_sizes> ...rest) {
     }
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/ir_emitter.cpp

@@ -8,8 +8,7 @@
 #include "frontend/A64/ir_emitter.h"
 #include "frontend/ir/opcodes.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 using Opcode = IR::Opcode;
 
@@ -134,5 +133,4 @@ void IREmitter::SetPC(const IR::U64& value) {
     Inst(Opcode::A64SetPC, value);
 }
 
-} // namespace IR
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/ir_emitter.h

@@ -16,8 +16,7 @@
 #include "frontend/ir/ir_emitter.h"
 #include "frontend/ir/value.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 /**
  * Convenience class to construct a basic block of the intermediate representation.
@@ -64,5 +63,4 @@ public:
     void SetPC(const IR::U64& value);
 };
 
-} // namespace IR
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/location_descriptor.cpp

@@ -9,13 +9,11 @@
 
 #include "frontend/A64/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 std::ostream& operator<<(std::ostream& o, const LocationDescriptor& loc) {
     o << fmt::format("{{{}, {}}}", loc.PC(), loc.FPCR().Value());
     return o;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/location_descriptor.h

@@ -15,8 +15,7 @@
 #include "frontend/A64/FPCR.h"
 #include "frontend/ir/location_descriptor.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 /**
  * LocationDescriptor describes the location of a basic block.
@@ -76,8 +75,7 @@ private:
  */
 std::ostream& operator<<(std::ostream& o, const LocationDescriptor& descriptor);
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic
 
 namespace std {
 template <>

src/frontend/A64/translate/impl/branch.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::B_cond(Imm<19> imm19, Cond cond) {
     s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();
@@ -127,5 +126,4 @@ bool TranslatorVisitor::TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
     return false;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_addsub.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
     size_t datasize = sf ? 64 : 32;
@@ -321,5 +320,4 @@ bool TranslatorVisitor::SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_bitfield.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 static IR::U32U64 ReplicateBit(IREmitter& ir, const IR::U32U64& value, u8 bit_position_to_replicate) {
     u8 datasize = value.GetType() == IR::Type::U64 ? 64 : 32;
@@ -77,5 +76,4 @@ bool TranslatorVisitor::UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn,
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_conditional_select.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::CSEL(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
     size_t datasize = sf ? 64 : 32;
@@ -58,5 +57,4 @@ bool TranslatorVisitor::CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_logical.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
     size_t datasize = sf ? 64 : 32;
@@ -212,5 +211,4 @@ bool TranslatorVisitor::BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn,
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_multiply.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::MADD(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
     const size_t datasize = sf ? 64 : 32;
@@ -103,5 +102,4 @@ bool TranslatorVisitor::SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_pcrel.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::ADR(Imm<2> immlo, Imm<19> immhi, Reg Rd) {
     u64 imm = concatenate(immhi, immlo).SignExtend<u64>();
@@ -23,5 +22,4 @@ bool TranslatorVisitor::ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_register.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::CLZ_int(bool sf, Reg Rn, Reg Rd) {
     const size_t datasize = sf ? 64 : 32;
@@ -113,5 +112,4 @@ bool TranslatorVisitor::REV16_int(bool sf, Reg Rn, Reg Rd) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/data_processing_shift.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 static IR::U8 SanitizeShiftAmount(TranslatorVisitor& tv, IREmitter& ir, size_t datasize,
                                   const IR::U32U64& amount) {
@@ -62,5 +61,4 @@ bool TranslatorVisitor::RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/exception_generating.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::SVC(Imm<16> imm16) {
     // ir.PushRSB(ir.current_location.AdvancePC(4)); // TODO
@@ -17,5 +16,4 @@ bool TranslatorVisitor::SVC(Imm<16> imm16) {
     return false;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/impl.cpp

@@ -8,8 +8,7 @@
 #include "frontend/ir/terminal.h"
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::InterpretThisInstruction() {
     ir.SetTerm(IR::Term::Interpret(ir.current_location));
@@ -304,5 +303,4 @@ IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option,
     return ir.LogicalShiftLeft(extended, ir.Imm8(shift));
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/impl.h

@@ -13,8 +13,7 @@
 #include "frontend/A64/location_descriptor.h"
 #include "frontend/A64/types.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 enum class AccType {
     NORMAL, VEC, STREAM, VECSTREAM, ATOMIC, ORDERED, UNPRIV, IFETCH, PTW, DC, IC, AT,
@@ -1029,5 +1028,4 @@ struct TranslatorVisitor final {
     bool FNMSUB_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd);
 };
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/load_store_load_literal.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
     size_t size = opc_0 == 0 ? 4 : 8;
@@ -39,5 +38,4 @@ bool TranslatorVisitor::PRFM_lit(Imm<19> /*imm19*/, Imm<5> /*prfop*/) {
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/load_store_register_immediate.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::load_store_register_immediate(bool wback, bool postindex, size_t scale, u64 offset, Imm<2> size, Imm<2> opc, Reg Rn, Reg Rt) {
     MemOp memop;
@@ -194,5 +193,4 @@ bool TranslatorVisitor::LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm1
     return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::LOAD, Rn, Vt);
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic

src/frontend/A64/translate/impl/load_store_register_pair.cpp

@@ -6,8 +6,7 @@
 
 #include "frontend/A64/translate/impl/impl.h"
 
-namespace Dynarmic {
+namespace Dynarmic::A64 {
-namespace A64 {
 
 bool TranslatorVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) {
     const bool postindex = !not_postindex;
@@ -75,5 +74,4 @@ bool TranslatorVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback,
     return true;
 }
 
-} // namespace A64
+} // namespace Dynarmic::A64
-} // namespace Dynarmic