A64: Implement FMADD
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2 changed files with 41 additions and 1 deletions
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@ -939,7 +939,7 @@ INST(FNMUL_float, "FNMUL (scalar)", "00011
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INST(FCSEL_float, "FCSEL", "00011110yy1mmmmmcccc11nnnnnddddd")
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// Data Processing - FP and SIMD - Floating point data processing three register
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//INST(FMADD_float, "FMADD", "00011111yy0mmmmm0aaaaannnnnddddd")
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INST(FMADD_float, "FMADD", "00011111yy0mmmmm0aaaaannnnnddddd")
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//INST(FMSUB_float, "FMSUB", "00011111yy0mmmmm1aaaaannnnnddddd")
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//INST(FNMADD_float, "FNMADD", "00011111yy1mmmmm0aaaaannnnnddddd")
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//INST(FNMSUB_float, "FNMSUB", "00011111yy1mmmmm1aaaaannnnnddddd")
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@ -0,0 +1,40 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <boost/optional.hpp>
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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static boost::optional<size_t> GetDataSize(Imm<2> type) {
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switch (type.ZeroExtend()) {
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case 0b00:
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return 32;
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case 0b01:
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return 64;
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case 0b11:
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// FP16Ext, unimplemented.
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return boost::none;
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}
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return boost::none;
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}
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bool TranslatorVisitor::FMADD_float(Imm<2> type, Vec Vm, Vec Va, Vec Vn, Vec Vd) {
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const auto datasize = GetDataSize(type);
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if (!datasize || *datasize == 16) {
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return UnallocatedEncoding();
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}
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const IR::U32U64 operanda = V_scalar(*datasize, Va);
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const IR::U32U64 operand1 = V_scalar(*datasize, Vn);
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const IR::U32U64 operand2 = V_scalar(*datasize, Vm);
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const IR::U32U64 result = ir.FPMulAdd(operanda, operand1, operand2, true);
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V_scalar(*datasize, Vd, result);
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return true;
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}
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} // namespace Dynarmic::A64
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