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frontend/ir_emitter: Add half-precision opcode for FPRecipStepFused

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Lioncash 2019-04-13 18:52:36 -04:00 committed by MerryMage
parent 68d8cd2b13
commit 6da0411111
5 changed files with 48 additions and 31 deletions
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6
src/backend/x64/emit_x64_floating_point.cpp
View file

@ -787,6 +787,7 @@ template<size_t fsize>
static void EmitFPRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
using FPT = mp::unsigned_integer_of_size<fsize>;
if constexpr (fsize != 16) {
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA)) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@ -822,6 +823,7 @@ static void EmitFPRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
ctx.reg_alloc.DefineValue(inst, result);
return;
}
}
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
ctx.reg_alloc.HostCall(inst, args[0], args[1]);
@ -830,6 +832,10 @@ static void EmitFPRecipStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
code.CallFunction(&FP::FPRecipStepFused<FPT>);
}
void EmitX64::EmitFPRecipStepFused16(EmitContext& ctx, IR::Inst* inst) {
EmitFPRecipStepFused<16>(code, ctx, inst);
}
void EmitX64::EmitFPRecipStepFused32(EmitContext& ctx, IR::Inst* inst) {
EmitFPRecipStepFused<32>(code, ctx, inst);
}

15
src/frontend/ir/ir_emitter.cpp
View file

@ -1943,11 +1943,20 @@ U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) {
}
}
U32U64 IREmitter::FPRecipStepFused(const U32U64& a, const U32U64& b) {
if (a.GetType() == Type::U32) {
U16U32U64 IREmitter::FPRecipStepFused(const U16U32U64& a, const U16U32U64& b) {
ASSERT(a.GetType() == b.GetType());
switch (a.GetType()) {
case Type::U16:
return Inst<U16>(Opcode::FPRecipStepFused16, a, b);
case Type::U32:
return Inst<U32>(Opcode::FPRecipStepFused32, a, b);
}
case Type::U64:
return Inst<U64>(Opcode::FPRecipStepFused64, a, b);
default:
UNREACHABLE();
return U16U32U64{};
}
}
U16U32U64 IREmitter::FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact) {

2
src/frontend/ir/ir_emitter.h
View file

@ -307,7 +307,7 @@ public:
U16U32U64 FPNeg(const U16U32U64& a);
U32U64 FPRecipEstimate(const U32U64& a);
U16U32U64 FPRecipExponent(const U16U32U64& a);
U32U64 FPRecipStepFused(const U32U64& a, const U32U64& b);
U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b);
U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact);
U32U64 FPRSqrtEstimate(const U32U64& a);
U32U64 FPRSqrtStepFused(const U32U64& a, const U32U64& b);

1
src/frontend/ir/microinstruction.cpp
View file

@ -277,6 +277,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPRecipExponent16:
case Opcode::FPRecipExponent32:
case Opcode::FPRecipExponent64:
case Opcode::FPRecipStepFused16:
case Opcode::FPRecipStepFused32:
case Opcode::FPRecipStepFused64:
case Opcode::FPRoundInt16:

1
src/frontend/ir/opcodes.inc
View file

@ -496,6 +496,7 @@ OPCODE(FPRecipEstimate64, U64, U64
OPCODE(FPRecipExponent16, U16, U16 )
OPCODE(FPRecipExponent32, U32, U32 )
OPCODE(FPRecipExponent64, U64, U64 )
OPCODE(FPRecipStepFused16, U16, U16, U16 )
OPCODE(FPRecipStepFused32, U32, U32, U32 )
OPCODE(FPRecipStepFused64, U64, U64, U64 )
OPCODE(FPRoundInt16, U16, U16, U8, U1 )