mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

fuzz_arm: Ensure all instructions are fuzzed

Browse source 
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
This commit is contained in:
MerryMage 2020-05-10 13:57:39 +01:00
parent 9a38c7324f
commit 6df660c889
5 changed files with 22 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/frontend/A32/decoder/arm.inc
View file

@ -121,6 +121,7 @@ INST(arm_SWPB, "SWPB", "cccc00010100nnnntttt00001001uuuu
INST(arm_LDRBT, "LDRBT (A1)", "----0100-111--------------------") INST(arm_LDRBT, "LDRBT (A1)", "----0100-111--------------------")
INST(arm_LDRBT, "LDRBT (A2)", "----0110-111---------------0----") INST(arm_LDRBT, "LDRBT (A2)", "----0110-111---------------0----")
INST(arm_LDRHT, "LDRHT (A1)", "----0000-111------------1011----") INST(arm_LDRHT, "LDRHT (A1)", "----0000-111------------1011----")
INST(arm_LDRHT, "LDRHT (A1)", "----0000-1111111--------1011----")
INST(arm_LDRHT, "LDRHT (A2)", "----0000-011--------00001011----") INST(arm_LDRHT, "LDRHT (A2)", "----0000-011--------00001011----")
INST(arm_LDRSBT, "LDRSBT (A1)", "----0000-111------------1101----") INST(arm_LDRSBT, "LDRSBT (A1)", "----0000-111------------1101----")
INST(arm_LDRSBT, "LDRSBT (A2)", "----0000-011--------00001101----") INST(arm_LDRSBT, "LDRSBT (A2)", "----0000-011--------00001101----")

1
src/frontend/A32/decoder/vfp.inc
View file

@ -49,6 +49,7 @@ INST(vfp_VPUSH, "VPUSH", "cccc11010D101101dddd101zv
INST(vfp_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv") // VFPv2 INST(vfp_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv") // VFPv2
INST(vfp_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv") // VFPv2 INST(vfp_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv") // VFPv2
INST(vfp_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv") // VFPv2 INST(vfp_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv") // VFPv2
INST(arm_UDF, "Undefined VSTM/VLDM", "----11000-0---------101---------") // VFPv2
INST(vfp_VSTM_a1, "VSTM (A1)", "cccc110puDw0nnnndddd1011vvvvvvvv") // VFPv2 INST(vfp_VSTM_a1, "VSTM (A1)", "cccc110puDw0nnnndddd1011vvvvvvvv") // VFPv2
INST(vfp_VSTM_a2, "VSTM (A2)", "cccc110puDw0nnnndddd1010vvvvvvvv") // VFPv2 INST(vfp_VSTM_a2, "VSTM (A2)", "cccc110puDw0nnnndddd1010vvvvvvvv") // VFPv2
INST(vfp_VLDM_a1, "VLDM (A1)", "cccc110puDw1nnnndddd1011vvvvvvvv") // VFPv2 INST(vfp_VLDM_a1, "VLDM (A1)", "cccc110puDw1nnnndddd1011vvvvvvvv") // VFPv2

24
src/frontend/A32/translate/impl/load_store.cpp
View file

@ -8,35 +8,43 @@
namespace Dynarmic::A32 { namespace Dynarmic::A32 {
bool ArmTranslatorVisitor::arm_LDRBT() { bool ArmTranslatorVisitor::arm_LDRBT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_LDRHT() { bool ArmTranslatorVisitor::arm_LDRHT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_LDRSBT() { bool ArmTranslatorVisitor::arm_LDRSBT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_LDRSHT() { bool ArmTranslatorVisitor::arm_LDRSHT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_LDRT() { bool ArmTranslatorVisitor::arm_LDRT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_STRBT() { bool ArmTranslatorVisitor::arm_STRBT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_STRHT() { bool ArmTranslatorVisitor::arm_STRHT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
bool ArmTranslatorVisitor::arm_STRT() { bool ArmTranslatorVisitor::arm_STRT() {
ASSERT_FALSE("System instructions unimplemented"); // System instructions unimplemented
return UndefinedInstruction();
} }
static IR::U32 GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::U32 offset) { static IR::U32 GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::U32 offset) {

3
src/frontend/A32/translate/impl/vfp.cpp
View file

@ -643,7 +643,9 @@ bool ArmTranslatorVisitor::vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8
return true; return true;
} }
const u32 imm32 = imm8.ZeroExtend() << 2;
auto address = ir.GetRegister(Reg::SP); auto address = ir.GetRegister(Reg::SP);
ir.SetRegister(Reg::SP, ir.Add(address, ir.Imm32(imm32)));
for (size_t i = 0; i < regs; ++i) { for (size_t i = 0; i < regs; ++i) {
if (sz) { if (sz) {
@ -662,7 +664,6 @@ bool ArmTranslatorVisitor::vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8
} }
} }
ir.SetRegister(Reg::SP, address);
return true; return true;
} }

3
tests/A32/fuzz_arm.cpp
View file

@ -123,9 +123,10 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) {
const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1); const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1);
const u32 inst = instructions.generators[index].Generate(); const u32 inst = instructions.generators[index].Generate();
if (std::any_of(instructions.invalid.begin(), instructions.invalid.end(), [inst](const auto& invalid) { return invalid.Match(inst); })) { if ((instructions.generators[index].Mask() & 0xF0000000) == 0 && (inst & 0xF0000000) == 0xF0000000) {
continue; continue;
} }
if (ShouldTestInst(inst, pc, is_last_inst)) { if (ShouldTestInst(inst, pc, is_last_inst)) {
return inst; return inst;
} }