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types: Add helpers for determining single and doubleword extension registers (#26)

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This commit is contained in:
Mat M 2016-09-07 07:08:35 -04:00 committed by Merry
parent 5bc9ce544f
commit 6e0f27a500
3 changed files with 32 additions and 20 deletions
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12
src/backend_x64/emit_x64.cpp
View file

@ -30,11 +30,11 @@ static Xbyak::Address MJitStateReg(Arm::Reg reg) {
static Xbyak::Address MJitStateExtReg(Arm::ExtReg reg) {
using namespace Xbyak::util;
if (reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31) {
if (Arm::IsSingleExtReg(reg)) {
size_t index = static_cast<size_t>(reg) - static_cast<size_t>(Arm::ExtReg::S0);
return dword[r15 + offsetof(JitState, ExtReg) + sizeof(u32) * index];
}
if (reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31) {
if (Arm::IsDoubleExtReg(reg)) {
size_t index = static_cast<size_t>(reg) - static_cast<size_t>(Arm::ExtReg::D0);
return qword[r15 + offsetof(JitState, ExtReg) + sizeof(u64) * index];
}
@ -112,7 +112,7 @@ void EmitX64::EmitGetRegister(IR::Block&, IR::Inst* inst) {
void EmitX64::EmitGetExtendedRegister32(IR::Block& block, IR::Inst* inst) {
Arm::ExtReg reg = inst->GetArg(0).GetExtRegRef();
ASSERT(reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31);
ASSERT(Arm::IsSingleExtReg(reg));
Xbyak::Xmm result = reg_alloc.DefXmm(inst);
code->movss(result, MJitStateExtReg(reg));
@ -120,7 +120,7 @@ void EmitX64::EmitGetExtendedRegister32(IR::Block& block, IR::Inst* inst) {
void EmitX64::EmitGetExtendedRegister64(IR::Block&, IR::Inst* inst) {
Arm::ExtReg reg = inst->GetArg(0).GetExtRegRef();
ASSERT(reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31);
ASSERT(Arm::IsDoubleExtReg(reg));
Xbyak::Xmm result = reg_alloc.DefXmm(inst);
code->movsd(result, MJitStateExtReg(reg));
}
@ -138,14 +138,14 @@ void EmitX64::EmitSetRegister(IR::Block&, IR::Inst* inst) {
void EmitX64::EmitSetExtendedRegister32(IR::Block&, IR::Inst* inst) {
Arm::ExtReg reg = inst->GetArg(0).GetExtRegRef();
ASSERT(reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31);
ASSERT(Arm::IsSingleExtReg(reg));
Xbyak::Xmm source = reg_alloc.UseXmm(inst->GetArg(1));
code->movss(MJitStateExtReg(reg), source);
}
void EmitX64::EmitSetExtendedRegister64(IR::Block&, IR::Inst* inst) {
Arm::ExtReg reg = inst->GetArg(0).GetExtRegRef();
ASSERT(reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31);
ASSERT(Arm::IsDoubleExtReg(reg));
Xbyak::Xmm source = reg_alloc.UseXmm(inst->GetArg(1));
code->movsd(MJitStateExtReg(reg), source);
}

24
src/frontend/arm/types.h
View file

@ -67,19 +67,29 @@ const char* RegToString(Reg reg);
const char* ExtRegToString(ExtReg reg);
std::string RegListToString(RegList reg_list);
constexpr bool IsSingleExtReg(ExtReg reg) {
return reg >= ExtReg::S0 && reg <= ExtReg::S31;
}
constexpr bool IsDoubleExtReg(ExtReg reg) {
return reg >= ExtReg::D0 && reg <= ExtReg::D31;
}
inline size_t RegNumber(Reg reg) {
ASSERT(reg != Reg::INVALID_REG);
return static_cast<size_t>(reg);
}
inline size_t RegNumber(ExtReg reg) {
if (reg >= ExtReg::S0 && reg <= ExtReg::S31) {
if (IsSingleExtReg(reg)) {
return static_cast<size_t>(reg) - static_cast<size_t>(ExtReg::S0);
} else if (reg >= ExtReg::D0 && reg <= ExtReg::D31) {
return static_cast<size_t>(reg) - static_cast<size_t>(ExtReg::D0);
} else {
ASSERT_MSG(false, "Invalid extended register");
}
if (IsDoubleExtReg(reg)) {
return static_cast<size_t>(reg) - static_cast<size_t>(ExtReg::D0);
}
ASSERT_MSG(false, "Invalid extended register");
}
inline Reg operator+(Reg reg, size_t number) {
@ -94,8 +104,8 @@ inline Reg operator+(Reg reg, size_t number) {
inline ExtReg operator+(ExtReg reg, size_t number) {
ExtReg new_reg = static_cast<ExtReg>(static_cast<size_t>(reg) + number);
ASSERT((reg >= ExtReg::S0 && reg <= ExtReg::S31 && new_reg >= ExtReg::S0 && new_reg <= ExtReg::S31)
|| (reg >= ExtReg::D0 && reg <= ExtReg::D31 && new_reg >= ExtReg::D0 && new_reg <= ExtReg::D31));
ASSERT((IsSingleExtReg(reg) && IsSingleExtReg(new_reg)) ||
(IsDoubleExtReg(reg) && IsDoubleExtReg(new_reg)));
return new_reg;
}

16
src/frontend/ir/ir_emitter.cpp
View file

@ -45,13 +45,15 @@ Value IREmitter::GetRegister(Arm::Reg reg) {
}
Value IREmitter::GetExtendedRegister(Arm::ExtReg reg) {
if (reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31) {
if (Arm::IsSingleExtReg(reg)) {
return Inst(Opcode::GetExtendedRegister32, {Value(reg)});
} else if (reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31) {
return Inst(Opcode::GetExtendedRegister64, {Value(reg)});
} else {
ASSERT_MSG(false, "Invalid reg.");
}
if (Arm::IsDoubleExtReg(reg)) {
return Inst(Opcode::GetExtendedRegister64, {Value(reg)});
}
ASSERT_MSG(false, "Invalid reg.");
}
void IREmitter::SetRegister(const Arm::Reg reg, const Value& value) {
@ -60,9 +62,9 @@ void IREmitter::SetRegister(const Arm::Reg reg, const Value& value) {
}
void IREmitter::SetExtendedRegister(const Arm::ExtReg reg, const Value& value) {
if (reg >= Arm::ExtReg::S0 && reg <= Arm::ExtReg::S31) {
if (Arm::IsSingleExtReg(reg)) {
Inst(Opcode::SetExtendedRegister32, {Value(reg), value});
} else if (reg >= Arm::ExtReg::D0 && reg <= Arm::ExtReg::D31) {
} else if (Arm::IsDoubleExtReg(reg)) {
Inst(Opcode::SetExtendedRegister64, {Value(reg), value});
} else {
ASSERT_MSG(false, "Invalid reg.");