thumb32: Implement AND (immediate)
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3 changed files with 21 additions and 2 deletions
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@ -54,7 +54,7 @@
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// Data Processing (Modified Immediate)
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INST(thumb32_TST_imm, "TST (imm)", "11110v000001nnnn0vvv1111vvvvvvvv")
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//INST(thumb32_AND_imm, "AND (imm)", "11110-00000-----0---------------")
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INST(thumb32_AND_imm, "AND (imm)", "11110v00000Snnnn0vvvddddvvvvvvvv")
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//INST(thumb32_BIC_imm, "BIC (imm)", "11110-00001-----0---------------")
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//INST(thumb32_MOV_imm, "MOV (imm)", "11110000010-11110---------------")
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//INST(thumb32_ORR_imm, "ORR (imm)", "11110-00010-----0---------------")
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@ -12,7 +12,7 @@ bool ThumbTranslatorVisitor::thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8
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return UnpredictableInstruction();
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}
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const auto imm_carry = ThumbExpandImm_C(rotate, imm8, ir.GetCFlag());
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const auto imm_carry = ThumbExpandImm_C(i, imm3, imm8, ir.GetCFlag());
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const auto result = ir.And(ir.GetRegister(n), ir.Imm32(imm_carry.imm32));
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ir.SetNFlag(ir.MostSignificantBit(result));
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@ -21,4 +21,22 @@ bool ThumbTranslatorVisitor::thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_AND_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
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ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
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if ((d == Reg::PC && !S) || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto imm_carry = ThumbExpandImm_C(i, imm3, imm8, ir.GetCFlag());
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const auto result = ir.And(ir.GetRegister(n), ir.Imm32(imm_carry.imm32));
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(imm_carry.carry);
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}
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return true;
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}
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} // namespace Dynarmic::A32
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@ -150,6 +150,7 @@ struct ThumbTranslatorVisitor final {
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// thumb32 data processing (modified immediate) instructions
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bool thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
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bool thumb32_AND_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
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// thumb32 miscellaneous control instructions
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bool thumb32_UDF();
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