Merge pull request #562 from emuplz/a64_ic_instructions
A64 IC Instructions
This commit is contained in:
commit
6f54c9d0b6
12 changed files with 101 additions and 14 deletions
|
@ -68,6 +68,15 @@ enum class DataCacheOperation {
|
||||||
ZeroByVA,
|
ZeroByVA,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum class InstructionCacheOperation {
|
||||||
|
/// IC IVAU
|
||||||
|
InvalidateByVAToPoU,
|
||||||
|
/// IC IALLU
|
||||||
|
InvalidateAllToPoU,
|
||||||
|
/// IC IALLUIS
|
||||||
|
InvalidateAllToPoUInnerSharable
|
||||||
|
};
|
||||||
|
|
||||||
struct UserCallbacks {
|
struct UserCallbacks {
|
||||||
virtual ~UserCallbacks() = default;
|
virtual ~UserCallbacks() = default;
|
||||||
|
|
||||||
|
@ -110,6 +119,7 @@ struct UserCallbacks {
|
||||||
|
|
||||||
virtual void ExceptionRaised(VAddr pc, Exception exception) = 0;
|
virtual void ExceptionRaised(VAddr pc, Exception exception) = 0;
|
||||||
virtual void DataCacheOperationRaised(DataCacheOperation /*op*/, VAddr /*value*/) {}
|
virtual void DataCacheOperationRaised(DataCacheOperation /*op*/, VAddr /*value*/) {}
|
||||||
|
virtual void InstructionCacheOperationRaised(InstructionCacheOperation /*op*/, VAddr /*value*/) {}
|
||||||
virtual void InstructionSynchronizationBarrierRaised() {}
|
virtual void InstructionSynchronizationBarrierRaised() {}
|
||||||
|
|
||||||
// Timing-related callbacks
|
// Timing-related callbacks
|
||||||
|
|
|
@ -234,6 +234,7 @@ if ("A64" IN_LIST DYNARMIC_FRONTENDS)
|
||||||
frontend/A64/translate/impl/simd_two_register_misc.cpp
|
frontend/A64/translate/impl/simd_two_register_misc.cpp
|
||||||
frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
|
frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
|
||||||
frontend/A64/translate/impl/sys_dc.cpp
|
frontend/A64/translate/impl/sys_dc.cpp
|
||||||
|
frontend/A64/translate/impl/sys_ic.cpp
|
||||||
frontend/A64/translate/impl/system.cpp
|
frontend/A64/translate/impl/system.cpp
|
||||||
frontend/A64/translate/impl/system_flag_format.cpp
|
frontend/A64/translate/impl/system_flag_format.cpp
|
||||||
frontend/A64/translate/impl/system_flag_manipulation.cpp
|
frontend/A64/translate/impl/system_flag_manipulation.cpp
|
||||||
|
|
|
@ -647,10 +647,16 @@ void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
||||||
|
|
||||||
void A64EmitX64::EmitA64DataCacheOperationRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
void A64EmitX64::EmitA64DataCacheOperationRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
||||||
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||||
ctx.reg_alloc.HostCall(nullptr, args[0], args[1]);
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
||||||
Devirtualize<&A64::UserCallbacks::DataCacheOperationRaised>(conf.callbacks).EmitCall(code);
|
Devirtualize<&A64::UserCallbacks::DataCacheOperationRaised>(conf.callbacks).EmitCall(code);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void A64EmitX64::EmitA64InstructionCacheOperationRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
||||||
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
||||||
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
||||||
|
Devirtualize<&A64::UserCallbacks::InstructionCacheOperationRaised>(conf.callbacks).EmitCall(code);
|
||||||
|
}
|
||||||
|
|
||||||
void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) {
|
void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) {
|
||||||
code.mfence();
|
code.mfence();
|
||||||
}
|
}
|
||||||
|
|
|
@ -108,6 +108,11 @@ INST(DC_CVAU, "DC CVAU", "11010
|
||||||
INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt")
|
INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt")
|
||||||
INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt")
|
INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt")
|
||||||
|
|
||||||
|
// SYS: Instruction Cache
|
||||||
|
INST(IC_IALLU, "IC IALLU", "11010101000010000111010100011111")
|
||||||
|
INST(IC_IALLUIS, "IC IALLUIS", "11010101000010000111000100011111")
|
||||||
|
INST(IC_IVAU, "IC IVAU", "110101010000101101110101001ttttt")
|
||||||
|
|
||||||
// Unconditional branch (Register)
|
// Unconditional branch (Register)
|
||||||
INST(BLR, "BLR", "1101011000111111000000nnnnn00000")
|
INST(BLR, "BLR", "1101011000111111000000nnnnn00000")
|
||||||
INST(BR, "BR", "1101011000011111000000nnnnn00000")
|
INST(BR, "BR", "1101011000011111000000nnnnn00000")
|
||||||
|
|
|
@ -56,6 +56,10 @@ void IREmitter::DataCacheOperationRaised(DataCacheOperation op, const IR::U64& v
|
||||||
Inst(Opcode::A64DataCacheOperationRaised, Imm64(static_cast<u64>(op)), value);
|
Inst(Opcode::A64DataCacheOperationRaised, Imm64(static_cast<u64>(op)), value);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void IREmitter::InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value) {
|
||||||
|
Inst(Opcode::A64InstructionCacheOperationRaised, Imm64(static_cast<u64>(op)), value);
|
||||||
|
}
|
||||||
|
|
||||||
void IREmitter::DataSynchronizationBarrier() {
|
void IREmitter::DataSynchronizationBarrier() {
|
||||||
Inst(Opcode::A64DataSynchronizationBarrier);
|
Inst(Opcode::A64DataSynchronizationBarrier);
|
||||||
}
|
}
|
||||||
|
|
|
@ -42,6 +42,7 @@ public:
|
||||||
void CallSupervisor(u32 imm);
|
void CallSupervisor(u32 imm);
|
||||||
void ExceptionRaised(Exception exception);
|
void ExceptionRaised(Exception exception);
|
||||||
void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
|
void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
|
||||||
|
void InstructionCacheOperationRaised(InstructionCacheOperation op, const IR::U64& value);
|
||||||
void DataSynchronizationBarrier();
|
void DataSynchronizationBarrier();
|
||||||
void DataMemoryBarrier();
|
void DataMemoryBarrier();
|
||||||
void InstructionSynchronizationBarrier();
|
void InstructionSynchronizationBarrier();
|
||||||
|
|
|
@ -174,6 +174,11 @@ struct TranslatorVisitor final {
|
||||||
bool DC_CVAP(Reg Rt);
|
bool DC_CVAP(Reg Rt);
|
||||||
bool DC_CIVAC(Reg Rt);
|
bool DC_CIVAC(Reg Rt);
|
||||||
|
|
||||||
|
// SYS: Instruction Cache
|
||||||
|
bool IC_IALLU();
|
||||||
|
bool IC_IALLUIS();
|
||||||
|
bool IC_IVAU(Reg Rt);
|
||||||
|
|
||||||
// Unconditional branch (Register)
|
// Unconditional branch (Register)
|
||||||
bool BR(Reg Rn);
|
bool BR(Reg Rn);
|
||||||
bool BRA(bool Z, bool M, Reg Rn, Reg Rm);
|
bool BRA(bool Z, bool M, Reg Rn, Reg Rm);
|
||||||
|
|
25
src/frontend/A64/translate/impl/sys_ic.cpp
Normal file
25
src/frontend/A64/translate/impl/sys_ic.cpp
Normal file
|
@ -0,0 +1,25 @@
|
||||||
|
/* This file is part of the dynarmic project.
|
||||||
|
* Copyright (c) 2018 MerryMage
|
||||||
|
* SPDX-License-Identifier: 0BSD
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "frontend/A64/translate/impl/impl.h"
|
||||||
|
|
||||||
|
namespace Dynarmic::A64 {
|
||||||
|
|
||||||
|
bool TranslatorVisitor::IC_IALLU() {
|
||||||
|
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoU, ir.Imm64(0));
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool TranslatorVisitor::IC_IALLUIS() {
|
||||||
|
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoUInnerSharable, ir.Imm64(0));
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool TranslatorVisitor::IC_IVAU(Reg Rt) {
|
||||||
|
ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateByVAToPoU, X(64, Rt));
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace Dynarmic::A64
|
|
@ -520,18 +520,19 @@ bool Inst::IsSetCheckBitOperation() const {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool Inst::MayHaveSideEffects() const {
|
bool Inst::MayHaveSideEffects() const {
|
||||||
return op == Opcode::PushRSB ||
|
return op == Opcode::PushRSB ||
|
||||||
op == Opcode::A64DataCacheOperationRaised ||
|
op == Opcode::A64DataCacheOperationRaised ||
|
||||||
IsSetCheckBitOperation() ||
|
op == Opcode::A64InstructionCacheOperationRaised ||
|
||||||
IsBarrier() ||
|
IsSetCheckBitOperation() ||
|
||||||
CausesCPUException() ||
|
IsBarrier() ||
|
||||||
WritesToCoreRegister() ||
|
CausesCPUException() ||
|
||||||
WritesToSystemRegister() ||
|
WritesToCoreRegister() ||
|
||||||
WritesToCPSR() ||
|
WritesToSystemRegister() ||
|
||||||
WritesToFPCR() ||
|
WritesToCPSR() ||
|
||||||
WritesToFPSR() ||
|
WritesToFPCR() ||
|
||||||
AltersExclusiveState() ||
|
WritesToFPSR() ||
|
||||||
IsMemoryWrite() ||
|
AltersExclusiveState() ||
|
||||||
|
IsMemoryWrite() ||
|
||||||
IsCoprocessorInstruction();
|
IsCoprocessorInstruction();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -69,6 +69,7 @@ A64OPC(SetPC, Void, U64
|
||||||
A64OPC(CallSupervisor, Void, U32 )
|
A64OPC(CallSupervisor, Void, U32 )
|
||||||
A64OPC(ExceptionRaised, Void, U64, U64 )
|
A64OPC(ExceptionRaised, Void, U64, U64 )
|
||||||
A64OPC(DataCacheOperationRaised, Void, U64, U64 )
|
A64OPC(DataCacheOperationRaised, Void, U64, U64 )
|
||||||
|
A64OPC(InstructionCacheOperationRaised, Void, U64, U64 )
|
||||||
A64OPC(DataSynchronizationBarrier, Void, )
|
A64OPC(DataSynchronizationBarrier, Void, )
|
||||||
A64OPC(DataMemoryBarrier, Void, )
|
A64OPC(DataMemoryBarrier, Void, )
|
||||||
A64OPC(InstructionSynchronizationBarrier, Void, )
|
A64OPC(InstructionSynchronizationBarrier, Void, )
|
||||||
|
|
|
@ -634,3 +634,31 @@ TEST_CASE("A64: Optimization failure when folding ADD", "[a64]") {
|
||||||
REQUIRE(jit.GetPstate() == 0x20000000);
|
REQUIRE(jit.GetPstate() == 0x20000000);
|
||||||
REQUIRE(jit.GetVector(30) == Vector{0xf7f6f5f4, 0});
|
REQUIRE(jit.GetVector(30) == Vector{0xf7f6f5f4, 0});
|
||||||
}
|
}
|
||||||
|
|
||||||
|
TEST_CASE("A64: Cache Maintenance Instructions", "[a64]") {
|
||||||
|
class CacheMaintenanceTestEnv final : public A64TestEnv {
|
||||||
|
void InstructionCacheOperationRaised(A64::InstructionCacheOperation op, VAddr value) override {
|
||||||
|
REQUIRE(op == A64::InstructionCacheOperation::InvalidateByVAToPoU);
|
||||||
|
REQUIRE(value == 0xcafed00d);
|
||||||
|
}
|
||||||
|
void DataCacheOperationRaised(A64::DataCacheOperation op, VAddr value) override {
|
||||||
|
REQUIRE(op == A64::DataCacheOperation::InvalidateByVAToPoC);
|
||||||
|
REQUIRE(value == 0xcafebabe);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
CacheMaintenanceTestEnv env;
|
||||||
|
A64::UserConfig conf{&env};
|
||||||
|
conf.hook_data_cache_operations = true;
|
||||||
|
A64::Jit jit{conf};
|
||||||
|
|
||||||
|
jit.SetRegister(0, 0xcafed00d);
|
||||||
|
jit.SetRegister(1, 0xcafebabe);
|
||||||
|
|
||||||
|
env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0
|
||||||
|
env.code_mem.emplace_back(0xd5087621); // dc ivac, x1
|
||||||
|
env.code_mem.emplace_back(0x14000000); // B .
|
||||||
|
|
||||||
|
env.ticks_left = 3;
|
||||||
|
jit.Run();
|
||||||
|
}
|
||||||
|
|
|
@ -15,7 +15,7 @@
|
||||||
|
|
||||||
using Vector = Dynarmic::A64::Vector;
|
using Vector = Dynarmic::A64::Vector;
|
||||||
|
|
||||||
class A64TestEnv final : public Dynarmic::A64::UserCallbacks {
|
class A64TestEnv : public Dynarmic::A64::UserCallbacks {
|
||||||
public:
|
public:
|
||||||
u64 ticks_left = 0;
|
u64 ticks_left = 0;
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue