Implement UXTAB16 (#78)
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2 changed files with 11 additions and 3 deletions
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@ -96,8 +96,16 @@ bool ArmTranslatorVisitor::arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation
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}
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bool ArmTranslatorVisitor::arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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bool ArmTranslatorVisitor::arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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UNUSED(cond, n, d, rotate, m);
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if (d == Reg::PC || m == Reg::PC || n == Reg::PC)
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return InterpretThisInstruction();
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto result = ir.And(rotated, ir.Imm32(0x00FF00FF));
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auto reg_n = ir.GetRegister(n);
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result = ir.PackedAddU16(reg_n, result).result;
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ir.SetRegister(d, result);
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}
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return true;
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}
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}
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bool ArmTranslatorVisitor::arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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bool ArmTranslatorVisitor::arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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@ -831,7 +831,7 @@ TEST_CASE("Fuzz ARM extension instructions", "[JitX64]") {
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InstructionGenerator("cccc011011001111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011011001111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011011111111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc011011111111ddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101110nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101110nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101100nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101100nnnnddddrr000111mmmm", is_valid), //UXTAB16
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InstructionGenerator("cccc01101111nnnnddddrr000111mmmm", is_valid),
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InstructionGenerator("cccc01101111nnnnddddrr000111mmmm", is_valid),
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}};
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}};
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