thumb32: Implement STMDB/STMFD
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3 changed files with 33 additions and 3 deletions
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@ -5,7 +5,7 @@ INST(thumb32_STMIA, "STMIA/STMEA", "1110100010W0nnnn0iiiii
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//INST(thumb32_POP, "POP", "1110100010111101----------------")
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//INST(thumb32_POP, "POP", "1110100010111101----------------")
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//INST(thumb32_LDMIA, "LDMIA/LDMFD", "1110100010-1--------------------")
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//INST(thumb32_LDMIA, "LDMIA/LDMFD", "1110100010-1--------------------")
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//INST(thumb32_PUSH, "PUSH", "1110100100101101----------------")
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//INST(thumb32_PUSH, "PUSH", "1110100100101101----------------")
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//INST(thumb32_STMDB, "STMDB/STMFD", "1110100100-0--------------------")
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INST(thumb32_STMDB, "STMDB/STMFD", "1110100100W0nnnn0iiiiiiiiiiiiiii")
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//INST(thumb32_LDMDB, "LDMDB/LDMEA", "1110100100-1--------------------")
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//INST(thumb32_LDMDB, "LDMDB/LDMEA", "1110100100-1--------------------")
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//INST(thumb32_SRS_1, "SRS", "1110100110-0--------------------")
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//INST(thumb32_SRS_1, "SRS", "1110100110-0--------------------")
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//INST(thumb32_RFE_2, "RFE", "1110100110-1--------------------")
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//INST(thumb32_RFE_2, "RFE", "1110100110-1--------------------")
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@ -26,10 +26,9 @@ bool ThumbTranslatorVisitor::thumb32_STMIA(bool W, Reg n, Imm<15> reg_list) {
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for (size_t i = 0; i < 15; i++) {
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for (size_t i = 0; i < 15; i++) {
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if (Common::Bit(i, regs_imm)) {
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if (Common::Bit(i, regs_imm)) {
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ir.WriteMemory32(address, ir.GetRegister(static_cast<Reg>(i)));
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ir.WriteMemory32(address, ir.GetRegister(static_cast<Reg>(i)));
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}
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address = ir.Add(address, ir.Imm32(4));
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address = ir.Add(address, ir.Imm32(4));
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}
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}
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}
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if (W) {
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if (W) {
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ir.SetRegister(n, address);
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ir.SetRegister(n, address);
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@ -37,4 +36,34 @@ bool ThumbTranslatorVisitor::thumb32_STMIA(bool W, Reg n, Imm<15> reg_list) {
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return true;
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return true;
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}
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}
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bool ThumbTranslatorVisitor::thumb32_STMDB(bool W, Reg n, Imm<15> reg_list) {
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const auto regs_imm = reg_list.ZeroExtend();
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const auto num_regs = static_cast<u32>(Common::BitCount(regs_imm));
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if (n == Reg::PC || num_regs < 2) {
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return UnpredictableInstruction();
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}
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if (W && Common::Bit(static_cast<size_t>(n), regs_imm)) {
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return UnpredictableInstruction();
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}
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if (reg_list.Bit<13>()) {
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return UnpredictableInstruction();
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}
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const IR::U32 start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(4 * num_regs));
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IR::U32 address = start_address;
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for (size_t i = 0; i < 15; i++) {
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if (Common::Bit(i, regs_imm)) {
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ir.WriteMemory32(address, ir.GetRegister(static_cast<Reg>(i)));
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address = ir.Add(address, ir.Imm32(4));
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}
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}
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if (W) {
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ir.SetRegister(n, start_address);
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}
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return true;
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}
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} // namespace Dynarmic::A32
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} // namespace Dynarmic::A32
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@ -173,6 +173,7 @@ struct ThumbTranslatorVisitor final {
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// thumb32 load/store multiple instructions
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// thumb32 load/store multiple instructions
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bool thumb32_STMIA(bool W, Reg n, Imm<15> reg_list);
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bool thumb32_STMIA(bool W, Reg n, Imm<15> reg_list);
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bool thumb32_STMDB(bool W, Reg n, Imm<15> reg_list);
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// thumb32 data processing (shifted register) instructions
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// thumb32 data processing (shifted register) instructions
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bool thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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