A64: Specialize arithmetic shift SBFM aliases
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a13392e432
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7242388577
4 changed files with 18 additions and 2 deletions
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@ -27,6 +27,8 @@ INST(MOVK, "MOVK", "z1110
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INST(SBFM, "SBFM", "z00100110Nrrrrrrssssssnnnnnddddd")
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INST(SBFM, "SBFM", "z00100110Nrrrrrrssssssnnnnnddddd")
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INST(BFM, "BFM", "z01100110Nrrrrrrssssssnnnnnddddd")
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INST(BFM, "BFM", "z01100110Nrrrrrrssssssnnnnnddddd")
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INST(UBFM, "UBFM", "z10100110Nrrrrrrssssssnnnnnddddd")
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INST(UBFM, "UBFM", "z10100110Nrrrrrrssssssnnnnnddddd")
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INST(ASR_1, "ASR (immediate, 32-bit)", "00010011000rrrrr011111nnnnnddddd")
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INST(ASR_2, "ASR (immediate, 64-bit)", "1001001101rrrrrr111111nnnnnddddd")
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INST(SXTB_1, "SXTB (32-bit)", "0001001100000000000111nnnnnddddd")
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INST(SXTB_1, "SXTB (32-bit)", "0001001100000000000111nnnnnddddd")
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INST(SXTB_2, "SXTB (64-bit)", "1001001101000000000111nnnnnddddd")
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INST(SXTB_2, "SXTB (64-bit)", "1001001101000000000111nnnnnddddd")
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INST(SXTH_1, "SXTH (32-bit)", "0001001100000000001111nnnnnddddd")
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INST(SXTH_1, "SXTH (32-bit)", "0001001100000000001111nnnnnddddd")
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@ -85,6 +85,20 @@ bool TranslatorVisitor::UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn,
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return true;
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return true;
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}
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}
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bool TranslatorVisitor::ASR_1(Imm<5> immr, Reg Rn, Reg Rd) {
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const auto src = X(32, Rn);
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const auto result = ir.ArithmeticShiftRightMasked(src, ir.Imm32(immr.ZeroExtend<u32>()));
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X(32, Rd, result);
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return true;
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}
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bool TranslatorVisitor::ASR_2(Imm<6> immr, Reg Rn, Reg Rd) {
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const auto src = X(64, Rn);
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const auto result = ir.ArithmeticShiftRightMasked(src, ir.Imm64(immr.ZeroExtend<u64>()));
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X(64, Rd, result);
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return true;
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}
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bool TranslatorVisitor::SXTB_1(Reg Rn, Reg Rd) {
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bool TranslatorVisitor::SXTB_1(Reg Rn, Reg Rd) {
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const auto src = X(32, Rn);
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const auto src = X(32, Rn);
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const auto result = ir.SignExtendToWord(ir.LeastSignificantByte(src));
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const auto result = ir.SignExtendToWord(ir.LeastSignificantByte(src));
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@ -94,6 +94,8 @@ struct TranslatorVisitor final {
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bool SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
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bool SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
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bool BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
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bool BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
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bool UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
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bool UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd);
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bool ASR_1(Imm<5> immr, Reg Rn, Reg Rd);
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bool ASR_2(Imm<6> immr, Reg Rn, Reg Rd);
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bool SXTB_1(Reg Rn, Reg Rd);
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bool SXTB_1(Reg Rn, Reg Rd);
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bool SXTB_2(Reg Rn, Reg Rd);
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bool SXTB_2(Reg Rn, Reg Rd);
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bool SXTH_1(Reg Rn, Reg Rd);
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bool SXTH_1(Reg Rn, Reg Rd);
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@ -12,12 +12,10 @@
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/ir_emitter.h"
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#include "frontend/ir/ir_emitter.h"
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#include "frontend/ir/opcodes.h"
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#include "frontend/ir/opcodes.h"
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#include "ir_opt/ir_matcher.h"
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#include "ir_opt/passes.h"
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#include "ir_opt/passes.h"
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namespace Dynarmic::Optimization {
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namespace Dynarmic::Optimization {
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using namespace IRMatcher;
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using Op = Dynarmic::IR::Opcode;
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using Op = Dynarmic::IR::Opcode;
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namespace {
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namespace {
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