types: Provide ostream operator<< overloads where applicable (#30)
This commit is contained in:
Mat M
Merry
parent
b41de890fb
commit
72897b5def
4 changed files with 270 additions and 249 deletions
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@ -5,6 +5,7 @@
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*/
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#include <array>
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#include <ostream>
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#include "common/bit_util.h"
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#include "frontend/arm/types.h"
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@ -50,5 +51,20 @@ std::string RegListToString(RegList reg_list) {
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return ret;
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}
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std::ostream& operator<<(std::ostream& o, Reg reg) {
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o << RegToString(reg);
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return o;
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}
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std::ostream& operator<<(std::ostream& o, ExtReg reg) {
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o << ExtRegToString(reg);
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return o;
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}
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std::ostream& operator<<(std::ostream& o, RegList reg_list) {
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o << RegListToString(reg_list);
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return o;
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}
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} // namespace Arm
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} // namespace Dynarmic
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@ -6,6 +6,7 @@
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#pragma once
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#include <iosfwd>
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#include <string>
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#include <utility>
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@ -67,6 +68,10 @@ const char* RegToString(Reg reg);
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const char* ExtRegToString(ExtReg reg);
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std::string RegListToString(RegList reg_list);
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std::ostream& operator<<(std::ostream& o, Reg reg);
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std::ostream& operator<<(std::ostream& o, ExtReg reg);
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std::ostream& operator<<(std::ostream& o, RegList reg_list);
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constexpr bool IsSingleExtReg(ExtReg reg) {
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return reg >= ExtReg::S0 && reg <= ExtReg::S31;
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}
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@ -52,13 +52,13 @@ public:
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std::string RsrStr(Reg s, ShiftType shift, Reg m) {
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switch (shift){
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case ShiftType::LSL:
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return fmt::format("{}, lsl {}", RegToString(m), RegToString(s));
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return fmt::format("{}, lsl {}", m, s);
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case ShiftType::LSR:
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return fmt::format("{}, lsr {}", RegToString(m), RegToString(s));
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return fmt::format("{}, lsr {}", m, s);
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case ShiftType::ASR:
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return fmt::format("{}, asr {}", RegToString(m), RegToString(s));
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return fmt::format("{}, asr {}", m, s);
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case ShiftType::ROR:
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return fmt::format("{}, ror {}", RegToString(m), RegToString(s));
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return fmt::format("{}, ror {}", m, s);
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}
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ASSERT(false);
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return "<internal error>";
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@ -69,11 +69,11 @@ public:
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case SignExtendRotation::ROR_0:
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return RegToString(m);
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case SignExtendRotation::ROR_8:
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return fmt::format("{}, ror #8", RegToString(m));
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return fmt::format("{}, ror #8", m);
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case SignExtendRotation::ROR_16:
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return fmt::format("{}, ror #16", RegToString(m));
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return fmt::format("{}, ror #16", m);
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case SignExtendRotation::ROR_24:
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return fmt::format("{}, ror #24", RegToString(m));
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return fmt::format("{}, ror #24", m);
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}
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ASSERT(false);
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return "<internal error>";
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@ -113,13 +113,13 @@ public:
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return fmt::format("blx {}#{}", Common::SignToChar(offset), abs(offset));
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}
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std::string arm_BLX_reg(Cond cond, Reg m) {
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return fmt::format("blx{} {}", CondToString(cond), RegToString(m));
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return fmt::format("blx{} {}", CondToString(cond), m);
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}
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std::string arm_BX(Cond cond, Reg m) {
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return fmt::format("bx{} {}", CondToString(cond), RegToString(m));
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return fmt::format("bx{} {}", CondToString(cond), m);
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}
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std::string arm_BXJ(Cond cond, Reg m) {
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return fmt::format("bxj{} {}", CondToString(cond), RegToString(m));
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return fmt::format("bxj{} {}", CondToString(cond), m);
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}
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// Coprocessor instructions
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@ -133,148 +133,148 @@ public:
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// Data processing instructions
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std::string arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("adc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("adc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("adc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("adc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("adc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("adc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("add{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("add{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("add{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("add{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("add{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("add{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("and{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("and{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("and{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("and{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("and{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("and{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("bic{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("bic{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("bic{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("bic{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("bic{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("bic{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return fmt::format("cmn{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("cmn{} {}, #{}", CondToString(cond), n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("cmn{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("cmn{} {}, {}{}", CondToString(cond), n, m, ShiftStr(shift, imm5));
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}
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std::string arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return fmt::format("cmn{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("cmn{} {}, {}", CondToString(cond), n, RsrStr(s, shift, m));
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}
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std::string arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return fmt::format("cmp{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("cmp{} {}, #{}", CondToString(cond), n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("cmp{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("cmp{} {}, {}{}", CondToString(cond), n, m, ShiftStr(shift, imm5));
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}
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std::string arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return fmt::format("cmp{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("cmp{} {}, {}", CondToString(cond), n, RsrStr(s, shift, m));
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}
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std::string arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("eor{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("eor{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("eor{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("eor{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("eor{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("eor{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("mov{}{} {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8));
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return fmt::format("mov{}{} {}, #{}", CondToString(cond), S ? "s" : "", d, ArmExpandImm(rotate, imm8));
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}
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std::string arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("mov{}{} {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("mov{}{} {}, {}{}", CondToString(cond), S ? "s" : "", d, m, ShiftStr(shift, imm5));
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}
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std::string arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("mov{}{} {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m));
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return fmt::format("mov{}{} {}, {}", CondToString(cond), S ? "s" : "", d, RsrStr(s, shift, m));
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}
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std::string arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("mvn{}{} {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8));
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return fmt::format("mvn{}{} {}, #{}", CondToString(cond), S ? "s" : "", d, ArmExpandImm(rotate, imm8));
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}
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std::string arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("mvn{}{} {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("mvn{}{} {}, {}{}", CondToString(cond), S ? "s" : "", d, m, ShiftStr(shift, imm5));
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}
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std::string arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("mvn{}{} {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m));
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return fmt::format("mvn{}{} {}, {}", CondToString(cond), S ? "s" : "", d, RsrStr(s, shift, m));
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}
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std::string arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("orr{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("orr{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("orr{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("orr{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("orr{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("orr{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("rsb{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("rsb{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("rsb{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("rsb{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("rsb{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("rsb{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("rsc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("rsc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("rsc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("rsc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("rsc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("rsc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("sbc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("sbc{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("sbc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("sbc{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("sbc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("sbc{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
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std::string arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return fmt::format("sub{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8));
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return fmt::format("sub{}{} {}, {}, #{}", CondToString(cond), S ? "s" : "", d, n, ArmExpandImm(rotate, imm8));
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}
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std::string arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return fmt::format("sub{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
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return fmt::format("sub{}{} {}, {}, {}{}", CondToString(cond), S ? "s" : "", d, n, m, ShiftStr(shift, imm5));
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}
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std::string arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return fmt::format("sub{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m));
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return fmt::format("sub{}{} {}, {}, {}", CondToString(cond), S ? "s" : "", d, n, RsrStr(s, shift, m));
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}
|
||||
std::string arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
return fmt::format("teq{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
|
||||
return fmt::format("teq{} {}, #{}", CondToString(cond), n, ArmExpandImm(rotate, imm8));
|
||||
}
|
||||
std::string arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return fmt::format("teq{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
|
||||
return fmt::format("teq{} {}, {}{}", CondToString(cond), n, m, ShiftStr(shift, imm5));
|
||||
}
|
||||
std::string arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return fmt::format("teq{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m));
|
||||
return fmt::format("teq{} {}, {}", CondToString(cond), n, RsrStr(s, shift, m));
|
||||
}
|
||||
std::string arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
return fmt::format("tst{} {}, #{}", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8));
|
||||
return fmt::format("tst{} {}, #{}", CondToString(cond), n, ArmExpandImm(rotate, imm8));
|
||||
}
|
||||
std::string arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return fmt::format("tst{} {}, {}{}", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5));
|
||||
return fmt::format("tst{} {}, {}{}", CondToString(cond), n, m, ShiftStr(shift, imm5));
|
||||
}
|
||||
std::string arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return fmt::format("tst{} {}, {}", CondToString(cond), RegToString(n), RsrStr(s, shift, m));
|
||||
return fmt::format("tst{} {}, {}", CondToString(cond), n, RsrStr(s, shift, m));
|
||||
}
|
||||
|
||||
// Exception generation instructions
|
||||
|
|
@ -290,40 +290,40 @@ public:
|
|||
|
||||
// Extension functions
|
||||
std::string arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("sxtab{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate));
|
||||
return fmt::format("sxtab{} {}, {}, {}", CondToString(cond), d, n, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("sxtab16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate));
|
||||
return fmt::format("sxtab16{} {}, {}, {}", CondToString(cond), d, n, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("sxtah{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate));
|
||||
return fmt::format("sxtah{} {}, {}, {}", CondToString(cond), d, n, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("sxtb{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate));
|
||||
return fmt::format("sxtb{} {}, {}", CondToString(cond), d, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("sxtb16{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate));
|
||||
return fmt::format("sxtb16{} {}, {}", CondToString(cond), d, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("sxth{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate));
|
||||
return fmt::format("sxth{} {}, {}", CondToString(cond), d, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("uxtab{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate));
|
||||
return fmt::format("uxtab{} {}, {}, {}", CondToString(cond), d, n, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("uxtab16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate));
|
||||
return fmt::format("uxtab16{} {}, {}, {}", CondToString(cond), d, n, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("uxtah{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RorStr(m, rotate));
|
||||
return fmt::format("uxtah{} {}, {}, {}", CondToString(cond), d, n, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_UXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("uxtb{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate));
|
||||
return fmt::format("uxtb{} {}, {}", CondToString(cond), d, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_UXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("uxtb16{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate));
|
||||
return fmt::format("uxtb16{} {}, {}", CondToString(cond), d, RorStr(m, rotate));
|
||||
}
|
||||
std::string arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
|
||||
return fmt::format("uxth{} {}, {}", CondToString(cond), RegToString(d), RorStr(m, rotate));
|
||||
return fmt::format("uxth{} {}, {}", CondToString(cond), d, RorStr(m, rotate));
|
||||
}
|
||||
|
||||
// Hint instructions
|
||||
|
|
@ -340,16 +340,16 @@ public:
|
|||
}
|
||||
std::string arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) {
|
||||
if (P) {
|
||||
return fmt::format("ldr{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : "");
|
||||
return fmt::format("ldr{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldr{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldr{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("ldr{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : "");
|
||||
return fmt::format("ldr{} {}, [{}, {}{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldr{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldr{} {}, [{}], {}{}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRB_lit(Cond cond, bool U, Reg t, Imm12 imm12) {
|
||||
|
|
@ -358,16 +358,16 @@ public:
|
|||
}
|
||||
std::string arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) {
|
||||
if (P) {
|
||||
return fmt::format("ldrb{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : "");
|
||||
return fmt::format("ldrb{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrb{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrb{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("ldrb{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : "");
|
||||
return fmt::format("ldrb{} {}, [{}, {}{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrb{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrb{} {}, [{}], {}{}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRBT() { return "ice"; }
|
||||
|
|
@ -378,16 +378,16 @@ public:
|
|||
std::string arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
u32 imm32 = (imm8a << 4) | imm8b;
|
||||
if (P) {
|
||||
return fmt::format("ldrd{} {}, {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? "!" : "");
|
||||
return fmt::format("ldrd{} {}, {}, [{}, #{}{}]{}", CondToString(cond), t, t+1, n, U ? '+' : '-', imm32, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrd{} {}, {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrd{} {}, {}, [{}], #{}{}{}", CondToString(cond), t, t+1, n, U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("ldrd{} {}, {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : "");
|
||||
return fmt::format("ldrd{} {}, {}, [{}, {}{}]{}", CondToString(cond), t, t+1, n, U ? '+' : '-', m, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrd{} {}, {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrd{} {}, {}, [{}], {}{}{}", CondToString(cond), t, t+1, n, U ? '+' : '-', m, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
|
|
@ -396,16 +396,16 @@ public:
|
|||
std::string arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
u32 imm32 = (imm8a << 4) | imm8b;
|
||||
if (P) {
|
||||
return fmt::format("ldrh{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : "");
|
||||
return fmt::format("ldrh{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrh{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrh{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("ldrd{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : "");
|
||||
return fmt::format("ldrd{} {}, [{}, {}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrd{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrd{} {}, [{}], {}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRHT() { return "ice"; }
|
||||
|
|
@ -416,16 +416,16 @@ public:
|
|||
std::string arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
u32 imm32 = (imm8a << 4) | imm8b;
|
||||
if (P) {
|
||||
return fmt::format("ldrsb{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : "");
|
||||
return fmt::format("ldrsb{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrsb{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrsb{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("ldrsb{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : "");
|
||||
return fmt::format("ldrsb{} {}, [{}, {}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrsb{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrsb{} {}, [{}], {}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRSBT() { return "ice"; }
|
||||
|
|
@ -436,77 +436,77 @@ public:
|
|||
std::string arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
u32 imm32 = (imm8a << 4) | imm8b;
|
||||
if (P) {
|
||||
return fmt::format("ldrsh{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : "");
|
||||
return fmt::format("ldrsh{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrsh{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrsh{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("ldrsh{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : "");
|
||||
return fmt::format("ldrsh{} {}, [{}, {}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("ldrsh{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("ldrsh{} {}, [{}], {}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_LDRSHT() { return "ice"; }
|
||||
std::string arm_LDRT() { return "ice"; }
|
||||
std::string arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) {
|
||||
if (P) {
|
||||
return fmt::format("str{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : "");
|
||||
return fmt::format("str{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("str{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("str{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("str{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : "");
|
||||
return fmt::format("str{} {}, [{}, {}{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("str{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("str{} {}, [{}], {}{}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm12 imm12) {
|
||||
if (P) {
|
||||
return fmt::format("strb{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? "!" : "");
|
||||
return fmt::format("strb{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("strb{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("strb{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm12, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("strb{} {}, [{}, {}{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? "!" : "");
|
||||
return fmt::format("strb{} {}, [{}, {}{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("strb{} {}, [{}], {}{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("strb{} {}, [{}], {}{}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, ShiftStr(shift, imm5), W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRBT() { return "ice"; }
|
||||
std::string arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
u32 imm32 = (imm8a << 4) | imm8b;
|
||||
if (P) {
|
||||
return fmt::format("strd{} {}, {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? "!" : "");
|
||||
return fmt::format("strd{} {}, {}, [{}, #{}{}]{}", CondToString(cond), t, t+1, n, U ? '+' : '-', imm32, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("strd{} {}, {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("strd{} {}, {}, [{}], #{}{}{}", CondToString(cond), t, t+1, n, U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("strd{} {}, {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : "");
|
||||
return fmt::format("strd{} {}, {}, [{}, {}{}]{}", CondToString(cond), t, t+1, n, U ? '+' : '-', m, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("strd{} {}, {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(t+1), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("strd{} {}, {}, [{}], {}{}{}", CondToString(cond), t, t+1, n, U ? '+' : '-', m, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm4 imm8a, Imm4 imm8b) {
|
||||
u32 imm32 = (imm8a << 4) | imm8b;
|
||||
if (P) {
|
||||
return fmt::format("strh{} {}, [{}, #{}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? "!" : "");
|
||||
return fmt::format("strh{} {}, [{}, #{}{}]{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("strh{} {}, [{}], #{}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("strh{} {}, [{}], #{}{}{}", CondToString(cond), t, n, U ? '+' : '-', imm32, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
||||
if (P) {
|
||||
return fmt::format("strd{} {}, [{}, {}{}]{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? "!" : "");
|
||||
return fmt::format("strd{} {}, [{}, {}{}]{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? "!" : "");
|
||||
} else {
|
||||
return fmt::format("strd{} {}, [{}], {}{}{}", CondToString(cond), RegToString(t), RegToString(n), U ? '+' : '-', RegToString(m), W ? " (err: W == 1!!!)" : "");
|
||||
return fmt::format("strd{} {}, [{}], {}{}{}", CondToString(cond), t, n, U ? '+' : '-', m, W ? " (err: W == 1!!!)" : "");
|
||||
}
|
||||
}
|
||||
std::string arm_STRHT() { return "ice"; }
|
||||
|
|
@ -514,158 +514,158 @@ public:
|
|||
|
||||
// Load/Store multiple instructions
|
||||
std::string arm_LDM(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("ldm{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("ldm{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_LDMDA(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("ldmda{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("ldmda{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_LDMDB(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("ldmdb{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("ldmdb{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_LDMIB(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("ldmib{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("ldmib{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_LDM_usr() { return "ice"; }
|
||||
std::string arm_LDM_eret() { return "ice"; }
|
||||
std::string arm_STM(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("stm{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("stm{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_STMDA(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("stmda{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("stmda{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_STMDB(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("stmdb{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("stmdb{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_STMIB(Cond cond, bool W, Reg n, RegList list) {
|
||||
return fmt::format("stmib{} {}{}, {{{}}}", CondToString(cond), RegToString(n), W ? "!" : "", RegListToString(list));
|
||||
return fmt::format("stmib{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list);
|
||||
}
|
||||
std::string arm_STM_usr() { return "ice"; }
|
||||
|
||||
// Miscellaneous instructions
|
||||
std::string arm_CLZ(Cond cond, Reg d, Reg m) {
|
||||
return fmt::format("clz{} {}, {}", CondToString(cond), RegToString(d), RegToString(m));
|
||||
return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
|
||||
}
|
||||
std::string arm_NOP() {
|
||||
return "nop";
|
||||
}
|
||||
std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("sel{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Unsigned sum of absolute difference functions
|
||||
std::string arm_USAD8(Cond cond, Reg d, Reg m, Reg n) {
|
||||
return fmt::format("usad8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("usad8{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_USADA8(Cond cond, Reg d, Reg a, Reg m, Reg n) {
|
||||
return fmt::format("usad8a{} {}, {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("usad8a{} {}, {}, {}, {}", CondToString(cond), d, n, m, a);
|
||||
}
|
||||
|
||||
// Packing instructions
|
||||
std::string arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) {
|
||||
return fmt::format("pkhbt{} {}, {}, {}{}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), ShiftStr(ShiftType::LSL, imm5));
|
||||
return fmt::format("pkhbt{} {}, {}, {}{}", CondToString(cond), d, n, m, ShiftStr(ShiftType::LSL, imm5));
|
||||
}
|
||||
std::string arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) {
|
||||
return fmt::format("pkhtb{} {}, {}, {}{}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), ShiftStr(ShiftType::ASR, imm5));
|
||||
return fmt::format("pkhtb{} {}, {}, {}{}", CondToString(cond), d, n, m, ShiftStr(ShiftType::ASR, imm5));
|
||||
}
|
||||
|
||||
// Reversal instructions
|
||||
std::string arm_REV(Cond cond, Reg d, Reg m) {
|
||||
return fmt::format("rev{} {}, {}", CondToString(cond), RegToString(d), RegToString(m));
|
||||
return fmt::format("rev{} {}, {}", CondToString(cond), d, m);
|
||||
}
|
||||
std::string arm_REV16(Cond cond, Reg d, Reg m) {
|
||||
return fmt::format("rev16{} {}, {}", CondToString(cond), RegToString(d), RegToString(m));
|
||||
return fmt::format("rev16{} {}, {}", CondToString(cond), d, m);
|
||||
}
|
||||
std::string arm_REVSH(Cond cond, Reg d, Reg m) {
|
||||
return fmt::format("revsh{} {}, {}", CondToString(cond), RegToString(d), RegToString(m));
|
||||
return fmt::format("revsh{} {}, {}", CondToString(cond), d, m);
|
||||
}
|
||||
|
||||
// Saturation instructions
|
||||
std::string arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
|
||||
return fmt::format("ssat{} {}, #{}, {}{}", CondToString(cond), RegToString(d), sat_imm + 1, RegToString(n), ShiftStr(ShiftType(sh << 1), imm5));
|
||||
return fmt::format("ssat{} {}, #{}, {}{}", CondToString(cond), d, sat_imm + 1, n, ShiftStr(ShiftType(sh << 1), imm5));
|
||||
}
|
||||
std::string arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
|
||||
return fmt::format("ssat16{} {}, #{}, {}", CondToString(cond), RegToString(d), sat_imm + 1, RegToString(n));
|
||||
return fmt::format("ssat16{} {}, #{}, {}", CondToString(cond), d, sat_imm + 1, n);
|
||||
}
|
||||
std::string arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
|
||||
return fmt::format("usat{} {}, #{}, {}{}", CondToString(cond), RegToString(d), sat_imm, RegToString(n), ShiftStr(ShiftType(sh << 1), imm5));
|
||||
return fmt::format("usat{} {}, #{}, {}{}", CondToString(cond), d, sat_imm, n, ShiftStr(ShiftType(sh << 1), imm5));
|
||||
}
|
||||
std::string arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
|
||||
return fmt::format("usat16{} {}, #{}, {}", CondToString(cond), RegToString(d), sat_imm, RegToString(n));
|
||||
return fmt::format("usat16{} {}, #{}, {}", CondToString(cond), d, sat_imm, n);
|
||||
}
|
||||
|
||||
// Multiply (Normal) instructions
|
||||
std::string arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) {
|
||||
return fmt::format("mla{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("mla{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) {
|
||||
return fmt::format("mul{}{} {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("mul{}{} {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Multiply (Long) instructions
|
||||
std::string arm_SMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
|
||||
return fmt::format("smlal{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("smlal{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_SMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
|
||||
return fmt::format("smull{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("smull{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_UMAAL(Cond cond, Reg dHi, Reg dLo, Reg m, Reg n) {
|
||||
return fmt::format("umaal{} {}, {}, {}, {}", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("umaal{} {}, {}, {}, {}", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_UMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
|
||||
return fmt::format("umlal{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("umlal{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_UMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
|
||||
return fmt::format("umull{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("umull{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
|
||||
// Multiply (Halfword) instructions
|
||||
std::string arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, bool N, Reg n) {
|
||||
return fmt::format("smlal{}{}{} {}, {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("smlal{}{}{} {}, {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bool N, Reg n) {
|
||||
return fmt::format("smla{}{}{} {}, {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("smla{}{}{} {}, {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, Reg n) {
|
||||
return fmt::format("smul{}{}{} {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("smul{}{}{} {}, {}, {}", N ? 't' : 'b', M ? 't' : 'b', CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Multiply (word by halfword) instructions
|
||||
std::string arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smlaw{}{} {}, {}, {}, {}", M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("smlaw{}{} {}, {}, {}, {}", M ? 't' : 'b', CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smulw{}{} {}, {}, {}", M ? 't' : 'b', CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("smulw{}{} {}, {}, {}", M ? 't' : 'b', CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Multiply (Most significant word) instructions
|
||||
std::string arm_SMMLA(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) {
|
||||
return fmt::format("smmla{}{} {}, {}, {}, {}", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("smmla{}{} {}, {}, {}, {}", R ? "r" : "", CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_SMMLS(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) {
|
||||
return fmt::format("smmls{}{} {}, {}, {}, {}", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("smmls{}{} {}, {}, {}, {}", R ? "r" : "", CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n) {
|
||||
return fmt::format("smmul{}{} {}, {}, {}", R ? "r" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("smmul{}{} {}, {}, {}", R ? "r" : "", CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Multiply (Dual) instructions
|
||||
std::string arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smlad{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("smlad{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smlald{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("smlald{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smlsd{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m), RegToString(a));
|
||||
return fmt::format("smlsd{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), d, n, m, a);
|
||||
}
|
||||
std::string arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smlsld{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(dLo), RegToString(dHi), RegToString(n), RegToString(m));
|
||||
return fmt::format("smlsld{}{} {}, {}, {}, {}", M ? "x" : "", CondToString(cond), dLo, dHi, n, m);
|
||||
}
|
||||
std::string arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smuad{}{} {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("smuad{}{} {}, {}, {}", M ? "x" : "", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) {
|
||||
return fmt::format("smusd{}{} {}, {}, {}", M ? "x" : "", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("smusd{}{} {}, {}, {}", M ? "x" : "", CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Parallel Add/Subtract (Modulo arithmetic) instructions
|
||||
|
|
@ -684,32 +684,32 @@ public:
|
|||
|
||||
// Parallel Add/Subtract (Saturating) instructions
|
||||
std::string arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("qadd8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("qadd8{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("qadd16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("qadd16{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_QASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("qsub8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("qsub8{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("qsub16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("qsub16{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_UQADD8(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("uqadd8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("uqadd8{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_UQADD16(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("uqadd16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("uqadd16{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_UQASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; }
|
||||
std::string arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("uqsub8{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("uqsub8{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
std::string arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("uqsub16{} {}, {}, {}", CondToString(cond), RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("uqsub16{} {}, {}, {}", CondToString(cond), d, n, m);
|
||||
}
|
||||
|
||||
// Parallel Add/Subtract (Halving) instructions
|
||||
|
|
@ -737,40 +737,40 @@ public:
|
|||
return "clrex";
|
||||
}
|
||||
std::string arm_LDREX(Cond cond, Reg n, Reg d) {
|
||||
return fmt::format("ldrex{} {}, [{}]", CondToString(cond), RegToString(d), RegToString(n));
|
||||
return fmt::format("ldrex{} {}, [{}]", CondToString(cond), d, n);
|
||||
}
|
||||
std::string arm_LDREXB(Cond cond, Reg n, Reg d) {
|
||||
return fmt::format("ldrexb{} {}, [{}]", CondToString(cond), RegToString(d), RegToString(n));
|
||||
return fmt::format("ldrexb{} {}, [{}]", CondToString(cond), d, n);
|
||||
}
|
||||
std::string arm_LDREXD(Cond cond, Reg n, Reg d) {
|
||||
return fmt::format("ldrexd{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(d+1), RegToString(n));
|
||||
return fmt::format("ldrexd{} {}, {}, [{}]", CondToString(cond), d, d+1, n);
|
||||
}
|
||||
std::string arm_LDREXH(Cond cond, Reg n, Reg d) {
|
||||
return fmt::format("ldrexh{} {}, [{}]", CondToString(cond), RegToString(d), RegToString(n));
|
||||
return fmt::format("ldrexh{} {}, [{}]", CondToString(cond), d, n);
|
||||
}
|
||||
std::string arm_STREX(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("strex{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n));
|
||||
return fmt::format("strex{} {}, {}, [{}]", CondToString(cond), d, m, n);
|
||||
}
|
||||
std::string arm_STREXB(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("strexb{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n));
|
||||
return fmt::format("strexb{} {}, {}, [{}]", CondToString(cond), d, m, n);
|
||||
}
|
||||
std::string arm_STREXD(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("strexd{} {}, {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(m+1), RegToString(n));
|
||||
return fmt::format("strexd{} {}, {}, {}, [{}]", CondToString(cond), d, m, m+1, n);
|
||||
}
|
||||
std::string arm_STREXH(Cond cond, Reg n, Reg d, Reg m) {
|
||||
return fmt::format("strexh{} {}, {}, [{}]", CondToString(cond), RegToString(d), RegToString(m), RegToString(n));
|
||||
return fmt::format("strexh{} {}, {}, [{}]", CondToString(cond), d, m, n);
|
||||
}
|
||||
std::string arm_SWP(Cond cond, Reg n, Reg t, Reg t2) {
|
||||
return fmt::format("swp{} {}, {}, [{}]", CondToString(cond), RegToString(t), RegToString(t2), RegToString(n));
|
||||
return fmt::format("swp{} {}, {}, [{}]", CondToString(cond), t, t2, n);
|
||||
}
|
||||
std::string arm_SWPB(Cond cond, Reg n, Reg t, Reg t2) {
|
||||
return fmt::format("swpb{} {}, {}, [{}]", CondToString(cond), RegToString(t), RegToString(t2), RegToString(n));
|
||||
return fmt::format("swpb{} {}, {}, [{}]", CondToString(cond), t, t2, n);
|
||||
}
|
||||
|
||||
// Status register access instructions
|
||||
std::string arm_CPS() { return "ice"; }
|
||||
std::string arm_MRS(Cond cond, Reg d) {
|
||||
return fmt::format("mrs{} {}, apsr", CondToString(cond), RegToString(d));
|
||||
return fmt::format("mrs{} {}, apsr", CondToString(cond), d);
|
||||
}
|
||||
std::string arm_MSR_imm(Cond cond, int mask, int rotate, Imm8 imm8) {
|
||||
bool write_nzcvq = Common::Bit<1>(mask);
|
||||
|
|
@ -780,7 +780,7 @@ public:
|
|||
std::string arm_MSR_reg(Cond cond, int mask, Reg n) {
|
||||
bool write_nzcvq = Common::Bit<1>(mask);
|
||||
bool write_g = Common::Bit<0>(mask);
|
||||
return fmt::format("msr{} apsr_{}{}, {}", CondToString(cond), write_nzcvq ? "nzcvq" : "", write_g ? "g" : "", RegToString(n));
|
||||
return fmt::format("msr{} apsr_{}{}, {}", CondToString(cond), write_nzcvq ? "nzcvq" : "", write_g ? "g" : "", n);
|
||||
}
|
||||
std::string arm_RFE() { return "ice"; }
|
||||
std::string arm_SETEND(bool E) {
|
||||
|
|
@ -826,35 +826,35 @@ public:
|
|||
}
|
||||
|
||||
std::string vfp2_VMOV_u32_f64(Cond cond, size_t Vd, Reg t, bool D){
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(true, Vd, D), RegToString(t));
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(true, Vd, D), t);
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_f64_u32(Cond cond, size_t Vn, Reg t, bool N){
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), RegToString(t), FPRegStr(true, Vn, N));
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(true, Vn, N));
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_u32_f32(Cond cond, size_t Vn, Reg t, bool N){
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(false, Vn, N), RegToString(t));
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), FPRegStr(false, Vn, N), t);
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_f32_u32(Cond cond, size_t Vn, Reg t, bool N){
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), RegToString(t), FPRegStr(false, Vn, N));
|
||||
return fmt::format("vmov{}.32 {}, {}", CondToString(cond), t, FPRegStr(false, Vn, N));
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_2u32_2f32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
|
||||
return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M), RegToString(t), RegToString(t2));
|
||||
return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M), t, t2);
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_2f32_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
|
||||
return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), RegToString(t), RegToString(t2), FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M));
|
||||
return fmt::format("vmov{} {}, {}, {}, {}", CondToString(cond), t, t2, FPRegStr(false, Vm, M), FPNextRegStr(false, Vm, M));
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_2u32_f64(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
|
||||
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), FPRegStr(true, Vm, M), RegToString(t), RegToString(t2));
|
||||
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), FPRegStr(true, Vm, M), t, t2);
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_f64_2u32(Cond cond, Reg t2, Reg t, bool M, size_t Vm){
|
||||
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), RegToString(t), RegToString(t2), FPRegStr(true, Vm, M));
|
||||
return fmt::format("vmov{} {}, {}, {}", CondToString(cond), t, t2, FPRegStr(true, Vm, M));
|
||||
}
|
||||
|
||||
std::string vfp2_VMOV_reg(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm){
|
||||
|
|
@ -890,13 +890,13 @@ public:
|
|||
}
|
||||
|
||||
std::string vfp2_VMSR(Cond cond, Reg t) {
|
||||
return fmt::format("vmsr{} fpscr, {}", CondToString(cond), RegToString(t));
|
||||
return fmt::format("vmsr{} fpscr, {}", CondToString(cond), t);
|
||||
}
|
||||
std::string vfp2_VMRS(Cond cond, Reg t) {
|
||||
if (t == Reg::R15) {
|
||||
return fmt::format("vmrs{} apsr_nzcv, fpscr", CondToString(cond));
|
||||
} else {
|
||||
return fmt::format("vmrs{} {}, fpscr", CondToString(cond), RegToString(t));
|
||||
return fmt::format("vmrs{} {}, fpscr", CondToString(cond), t);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -910,40 +910,40 @@ public:
|
|||
|
||||
std::string vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
|
||||
u32 imm32 = imm8 << 2;
|
||||
return fmt::format("vldr{} {}, [{}, #{}{}]", CondToString(cond), FPRegStr(sz, Vd, D), RegToString(n), U ? '+' : '-', imm32);
|
||||
return fmt::format("vldr{} {}, [{}, #{}{}]", CondToString(cond), FPRegStr(sz, Vd, D), n, U ? '+' : '-', imm32);
|
||||
}
|
||||
|
||||
std::string vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
|
||||
u32 imm32 = imm8 << 2;
|
||||
return fmt::format("vstr{} {}, [{}, #{}{}]", CondToString(cond), FPRegStr(sz, Vd, D), RegToString(n), U ? '+' : '-', imm32);
|
||||
return fmt::format("vstr{} {}, [{}, #{}{}]", CondToString(cond), FPRegStr(sz, Vd, D), n, U ? '+' : '-', imm32);
|
||||
}
|
||||
|
||||
std::string vfp2_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
||||
const char* mode = "<invalid mode>";
|
||||
if (!p && u) mode = "ia";
|
||||
if (p && !u) mode = "db";
|
||||
return fmt::format("vstm{}{}.f64 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D), imm8);
|
||||
return fmt::format("vstm{}{}.f64 {}{}, {}(+{})", mode, CondToString(cond), n, w ? "!" : "", FPRegStr(true, Vd, D), imm8);
|
||||
}
|
||||
|
||||
std::string vfp2_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
||||
const char* mode = "<invalid mode>";
|
||||
if (!p && u) mode = "ia";
|
||||
if (p && !u) mode = "db";
|
||||
return fmt::format("vstm{}{}.f32 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D), imm8);
|
||||
return fmt::format("vstm{}{}.f32 {}{}, {}(+{})", mode, CondToString(cond), n, w ? "!" : "", FPRegStr(false, Vd, D), imm8);
|
||||
}
|
||||
|
||||
std::string vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
||||
const char* mode = "<invalid mode>";
|
||||
if (!p && u) mode = "ia";
|
||||
if (p && !u) mode = "db";
|
||||
return fmt::format("vldm{}{}.f64 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D), imm8);
|
||||
return fmt::format("vldm{}{}.f64 {}{}, {}(+{})", mode, CondToString(cond), n, w ? "!" : "", FPRegStr(true, Vd, D), imm8);
|
||||
}
|
||||
|
||||
std::string vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
|
||||
const char* mode = "<invalid mode>";
|
||||
if (!p && u) mode = "ia";
|
||||
if (p && !u) mode = "db";
|
||||
return fmt::format("vldm{}{}.f32 {}{}, {}(+{})", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D), imm8);
|
||||
return fmt::format("vldm{}{}.f32 {}{}, {}(+{})", mode, CondToString(cond), n, w ? "!" : "", FPRegStr(false, Vd, D), imm8);
|
||||
}
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,210 +20,210 @@ namespace Arm {
|
|||
class DisassemblerVisitor {
|
||||
public:
|
||||
std::string thumb16_LSL_imm(Imm5 imm5, Reg m, Reg d) {
|
||||
return fmt::format("lsls {}, {}, #{}", RegToString(d), RegToString(m), imm5);
|
||||
return fmt::format("lsls {}, {}, #{}", d, m, imm5);
|
||||
}
|
||||
|
||||
std::string thumb16_LSR_imm(Imm5 imm5, Reg m, Reg d) {
|
||||
return fmt::format("lsrs {}, {}, #{}", RegToString(d), RegToString(m), imm5 != 0 ? imm5 : 32);
|
||||
return fmt::format("lsrs {}, {}, #{}", d, m, imm5 != 0 ? imm5 : 32);
|
||||
}
|
||||
|
||||
std::string thumb16_ASR_imm(Imm5 imm5, Reg m, Reg d) {
|
||||
return fmt::format("asrs {}, {}, #{}", RegToString(d), RegToString(m), imm5 != 0 ? imm5 : 32);
|
||||
return fmt::format("asrs {}, {}, #{}", d, m, imm5 != 0 ? imm5 : 32);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) {
|
||||
return fmt::format("adds {}, {}, {}", RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("adds {}, {}, {}", d, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) {
|
||||
return fmt::format("subs {}, {}, {}", RegToString(d), RegToString(n), RegToString(m));
|
||||
return fmt::format("subs {}, {}, {}", d, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
|
||||
return fmt::format("adds {}, {}, #{}", RegToString(d), RegToString(n), imm3);
|
||||
return fmt::format("adds {}, {}, #{}", d, n, imm3);
|
||||
}
|
||||
|
||||
std::string thumb16_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
|
||||
return fmt::format("subs {}, {}, #{}", RegToString(d), RegToString(n), imm3);
|
||||
return fmt::format("subs {}, {}, #{}", d, n, imm3);
|
||||
}
|
||||
|
||||
std::string thumb16_MOV_imm(Reg d, Imm8 imm8) {
|
||||
return fmt::format("movs {}, #{}", RegToString(d), imm8);
|
||||
return fmt::format("movs {}, #{}", d, imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_CMP_imm(Reg n, Imm8 imm8) {
|
||||
return fmt::format("cmp {}, #{}", RegToString(n), imm8);
|
||||
return fmt::format("cmp {}, #{}", n, imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_imm_t2(Reg d_n, Imm8 imm8) {
|
||||
return fmt::format("adds {}, #{}", RegToString(d_n), imm8);
|
||||
return fmt::format("adds {}, #{}", d_n, imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_SUB_imm_t2(Reg d_n, Imm8 imm8) {
|
||||
return fmt::format("subs {}, #{}", RegToString(d_n), imm8);
|
||||
return fmt::format("subs {}, #{}", d_n, imm8);
|
||||
}
|
||||
|
||||
std::string thumb16_AND_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("ands {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("ands {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_EOR_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("eors {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("eors {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LSL_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("lsls {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("lsls {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LSR_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("lsrs {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("lsrs {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_ASR_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("asrs {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("asrs {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_ADC_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("adcs {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("adcs {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_SBC_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("sbcs {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("sbcs {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_ROR_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("rors {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("rors {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_TST_reg(Reg m, Reg n) {
|
||||
return fmt::format("tst {}, {}", RegToString(n), RegToString(m));
|
||||
return fmt::format("tst {}, {}", n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_RSB_imm(Reg n, Reg d) {
|
||||
// Pre-UAL syntax: NEGS <Rd>, <Rn>
|
||||
return fmt::format("rsbs {}, {}, #0", RegToString(d), RegToString(n));
|
||||
return fmt::format("rsbs {}, {}, #0", d, n);
|
||||
}
|
||||
|
||||
std::string thumb16_CMP_reg_t1(Reg m, Reg n) {
|
||||
return fmt::format("cmp {}, {}", RegToString(n), RegToString(m));
|
||||
return fmt::format("cmp {}, {}", n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_CMN_reg(Reg m, Reg n) {
|
||||
return fmt::format("cmn {}, {}", RegToString(n), RegToString(m));
|
||||
return fmt::format("cmn {}, {}", n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_ORR_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("orrs {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("orrs {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_BIC_reg(Reg m, Reg d_n) {
|
||||
return fmt::format("bics {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("bics {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_MVN_reg(Reg m, Reg d) {
|
||||
return fmt::format("mvns {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("mvns {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
|
||||
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
|
||||
return fmt::format("add {}, {}", RegToString(d_n), RegToString(m));
|
||||
return fmt::format("add {}, {}", d_n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
|
||||
Reg n = n_hi ? (n_lo + 8) : n_lo;
|
||||
return fmt::format("cmp {}, {}", RegToString(n), RegToString(m));
|
||||
return fmt::format("cmp {}, {}", n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
|
||||
Reg d = d_hi ? (d_lo + 8) : d_lo;
|
||||
return fmt::format("mov {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("mov {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LDR_literal(Reg t, Imm8 imm8) {
|
||||
u32 imm32 = imm8 << 2;
|
||||
return fmt::format("ldr {}, [pc, #{}]", RegToString(t), imm32);
|
||||
return fmt::format("ldr {}, [pc, #{}]", t, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_STR_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("str {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("str {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("strh {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("strh {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("strb {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("strb {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LDRSB_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("ldrsb {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("ldrsb {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LDR_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("ldr {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("ldr {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LDRH_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("ldrh {}, [%s, %s]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("ldrh {}, [%s, %s]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LDRB_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("ldrb {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("ldrb {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_LDRSH_reg(Reg m, Reg n, Reg t) {
|
||||
return fmt::format("ldrsh {}, [{}, {}]", RegToString(t), RegToString(n), RegToString(m));
|
||||
return fmt::format("ldrsh {}, [{}, {}]", t, n, m);
|
||||
}
|
||||
|
||||
std::string thumb16_STR_imm_t1(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5 << 2;
|
||||
return fmt::format("str {}, [{}, #{}]", RegToString(t), RegToString(n), imm32);
|
||||
return fmt::format("str {}, [{}, #{}]", t, n, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5 << 2;
|
||||
return fmt::format("ldr {}, [{}, #{}]", RegToString(t), RegToString(n), imm32);
|
||||
return fmt::format("ldr {}, [{}, #{}]", t, n, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_STRB_imm(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5;
|
||||
return fmt::format("strb {}, [{}, #{}]", RegToString(t), RegToString(n), imm32);
|
||||
return fmt::format("strb {}, [{}, #{}]", t, n, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_LDRB_imm(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5;
|
||||
return fmt::format("ldrb {}, [{}, #{}]", RegToString(t), RegToString(n), imm32);
|
||||
return fmt::format("ldrb {}, [{}, #{}]", t, n, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_STRH_imm(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5 << 1;
|
||||
return fmt::format("strh {}, [{}, #{}]", RegToString(t), RegToString(n), imm32);
|
||||
return fmt::format("strh {}, [{}, #{}]", t, n, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_LDRH_imm(Imm5 imm5, Reg n, Reg t) {
|
||||
u32 imm32 = imm5 << 1;
|
||||
return fmt::format("ldrh {}, [{}, #{}]", RegToString(t), RegToString(n), imm32);
|
||||
return fmt::format("ldrh {}, [{}, #{}]", t, n, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_STR_imm_t2(Reg t, Imm5 imm5) {
|
||||
u32 imm32 = imm5 << 2;
|
||||
return fmt::format("str {}, [sp, #{}]", RegToString(t), imm32);
|
||||
return fmt::format("str {}, [sp, #{}]", t, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_LDR_imm_t2(Reg t, Imm5 imm5) {
|
||||
u32 imm32 = imm5 << 2;
|
||||
return fmt::format("ldr {}, [sp, #{}]", RegToString(t), imm32);
|
||||
return fmt::format("ldr {}, [sp, #{}]", t, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_ADR(Reg d, Imm8 imm8) {
|
||||
u32 imm32 = imm8 << 2;
|
||||
return fmt::format("adr {}, +#{}", RegToString(d), imm32);
|
||||
return fmt::format("adr {}, +#{}", d, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_sp_t1(Reg d, Imm8 imm8) {
|
||||
u32 imm32 = imm8 << 2;
|
||||
return fmt::format("add {}, sp, #{}", RegToString(d), imm32);
|
||||
return fmt::format("add {}, sp, #{}", d, imm32);
|
||||
}
|
||||
|
||||
std::string thumb16_ADD_sp_t2(Imm7 imm7) {
|
||||
|
|
@ -237,29 +237,29 @@ public:
|
|||
}
|
||||
|
||||
std::string thumb16_SXTH(Reg m, Reg d) {
|
||||
return fmt::format("sxth {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("sxth {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_SXTB(Reg m, Reg d) {
|
||||
return fmt::format("sxtb {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("sxtb {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_UXTH(Reg m, Reg d) {
|
||||
return fmt::format("uxth {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("uxth {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_UXTB(Reg m, Reg d) {
|
||||
return fmt::format("uxtb {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("uxtb {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_PUSH(bool M, RegList reg_list) {
|
||||
if (M) reg_list |= 1 << 14;
|
||||
return "push " + RegListToString(reg_list);
|
||||
return fmt::format("push {}", reg_list);
|
||||
}
|
||||
|
||||
std::string thumb16_POP(bool P, RegList reg_list) {
|
||||
if (P) reg_list |= 1 << 15;
|
||||
return "pop " + RegListToString(reg_list);
|
||||
return fmt::format("pop {}", reg_list);
|
||||
}
|
||||
|
||||
std::string thumb16_SETEND(bool E) {
|
||||
|
|
@ -267,32 +267,32 @@ public:
|
|||
}
|
||||
|
||||
std::string thumb16_REV(Reg m, Reg d) {
|
||||
return fmt::format("rev {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("rev {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_REV16(Reg m, Reg d) {
|
||||
return fmt::format("rev16 {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("rev16 {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_REVSH(Reg m, Reg d) {
|
||||
return fmt::format("revsh {}, {}", RegToString(d), RegToString(m));
|
||||
return fmt::format("revsh {}, {}", d, m);
|
||||
}
|
||||
|
||||
std::string thumb16_STMIA(Reg n, RegList reg_list) {
|
||||
return fmt::format("stm {}!, {}", RegToString(n), RegListToString(reg_list));
|
||||
return fmt::format("stm {}!, {}", n, reg_list);
|
||||
}
|
||||
|
||||
std::string thumb16_LDMIA(Reg n, RegList reg_list) {
|
||||
bool write_back = !Common::Bit(static_cast<size_t>(n), reg_list);
|
||||
return fmt::format("ldm {}{}, {}", RegToString(n), write_back ? "!" : "", RegListToString(reg_list));
|
||||
return fmt::format("ldm {}{}, {}", n, write_back ? "!" : "", reg_list);
|
||||
}
|
||||
|
||||
std::string thumb16_BX(Reg m) {
|
||||
return fmt::format("bx {}", RegToString(m));
|
||||
return fmt::format("bx {}", m);
|
||||
}
|
||||
|
||||
std::string thumb16_BLX_reg(Reg m) {
|
||||
return fmt::format("blx {}", RegToString(m));
|
||||
return fmt::format("blx {}", m);
|
||||
}
|
||||
|
||||
std::string thumb16_UDF() {
|
||||
|
|
|
|||
Loading…
Reference in a new issue