mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement SQNEG's scalar and vector variant

Browse source
This commit is contained in:
Lioncash 2018-09-06 16:47:27 -04:00 committed by MerryMage
parent fca7eddb9e
commit 740ffa52ae
3 changed files with 27 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/frontend/A64/decoder/a64.inc
View file

@ -414,7 +414,7 @@ INST(CMLT_1, "CMLT (zero)", "01011
INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd") INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd")
INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd") INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd")
//INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd") //INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd")
//INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd") INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd")
INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd") INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd")
INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd") INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd")
INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd") INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd")
@ -618,7 +618,7 @@ INST(UADDLP, "UADDLP", "0Q101
//INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd") //INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")
//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd") //INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd") INST(UADALP, "UADALP", "0Q101110zz100000011010nnnnnddddd")
//INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd") INST(SQNEG_2, "SQNEG", "0Q101110zz100000011110nnnnnddddd")
INST(CMGE_zero_2, "CMGE (zero)", "0Q101110zz100000100010nnnnnddddd") INST(CMGE_zero_2, "CMGE (zero)", "0Q101110zz100000100010nnnnnddddd")
INST(CMLE_2, "CMLE (zero)", "0Q101110zz100000100110nnnnnddddd") INST(CMLE_2, "CMLE (zero)", "0Q101110zz100000100110nnnnnddddd")
INST(NEG_2, "NEG (vector)", "0Q101110zz100000101110nnnnnddddd") INST(NEG_2, "NEG (vector)", "0Q101110zz100000101110nnnnnddddd")

10
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -215,6 +215,16 @@ bool TranslatorVisitor::SQABS_1(Imm<2> size, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::SQNEG_1(Imm<2> size, Vec Vn, Vec Vd) {
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand = ir.ZeroExtendToQuad(ir.VectorGetElement(esize, V(128, Vn), 0));
const IR::U128 result = ir.VectorSignedSaturatedNeg(esize, operand);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) { bool TranslatorVisitor::SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToSigned); return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToSigned);
} }

15
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -614,6 +614,21 @@ bool TranslatorVisitor::SQABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::SQNEG_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.VectorSignedSaturatedNeg(esize, operand);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) { bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate); return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate);
} }