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A64: Implement CMEQ (register, vector)

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This commit is contained in:
MerryMage 2018-01-26 01:52:42 +00:00
parent d5283e46e8
commit 75756137c6
2 changed files with 31 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -587,7 +587,7 @@ INST(ADD_vector, "ADD (vector)", "0Q001
//INST(SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd")
//INST(SUB_2, "SUB (vector)", "0Q101110zz1mmmmm100001nnnnnddddd")
//INST(CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd")
//INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")
INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")
//INST(SQRDMULH_vec_1, "SQRDMULH (vector)", "01111110zz1mmmmm101101nnnnnddddd")
//INST(SQRDMULH_vec_2, "SQRDMULH (vector)", "0Q101110zz1mmmmm101101nnnnnddddd")

30
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -35,6 +35,36 @@ bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd)
return true;
}
bool TranslatorVisitor::CMEQ_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
IR::U128 result = [&]{
switch (esize) {
case 8:
return ir.VectorEqual8(operand1, operand2);
case 16:
return ir.VectorEqual16(operand1, operand2);
case 32:
return ir.VectorEqual32(operand1, operand2);
default:
return ir.VectorEqual64(operand1, operand2);
}
}();
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::ADDP_vec(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();