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implemented other ic instructions

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This commit is contained in:
rufi 2020-11-09 09:01:20 +00:00 committed by MerryMage
parent 8728444af8
commit 77621a8448
4 changed files with 24 additions and 38 deletions
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6
include/dynarmic/A64/config.h
View file

@ -69,8 +69,12 @@ enum class DataCacheOperation {
}; };
enum class InstructionCacheOperation { enum class InstructionCacheOperation {
// IC IVAU /// IC IVAU
InvalidateByVAToPoU, InvalidateByVAToPoU,
/// IC IALLU
InvalidateAllToPoU,
/// IC IALLUIS
InvalidateAllToPoUInnerSharable
}; };
struct UserCallbacks { struct UserCallbacks {

14
src/frontend/A64/translate/impl/sys_ic.cpp
View file

@ -7,21 +7,19 @@
namespace Dynarmic::A64 { namespace Dynarmic::A64 {
static bool InstructionCacheInstruction(TranslatorVisitor& v, InstructionCacheOperation op, const Reg Rt) { bool TranslatorVisitor::IC_IALLU() {
v.ir.InstructionCacheOperationRaised(op, v.X(64, Rt)); ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoU, ir.Imm64(0));
return true; return true;
} }
bool TranslatorVisitor::IC_IALLU() {
return false;
}
bool TranslatorVisitor::IC_IALLUIS() { bool TranslatorVisitor::IC_IALLUIS() {
return false; ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateAllToPoUInnerSharable, ir.Imm64(0));
return true;
} }
bool TranslatorVisitor::IC_IVAU(Reg Rt) { bool TranslatorVisitor::IC_IVAU(Reg Rt) {
return InstructionCacheInstruction(*this, InstructionCacheOperation::InvalidateByVAToPoU, Rt); ir.InstructionCacheOperationRaised(InstructionCacheOperation::InvalidateByVAToPoU, X(64, Rt));
return true;
} }
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64

25
src/frontend/ir/microinstruction.cpp
View file

@ -520,18 +520,19 @@ bool Inst::IsSetCheckBitOperation() const {
} }
bool Inst::MayHaveSideEffects() const { bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB || return op == Opcode::PushRSB ||
op == Opcode::A64DataCacheOperationRaised || op == Opcode::A64DataCacheOperationRaised ||
IsSetCheckBitOperation() || op == Opcode::A64InstructionCacheOperationRaised ||
IsBarrier() || IsSetCheckBitOperation() ||
CausesCPUException() || IsBarrier() ||
WritesToCoreRegister() || CausesCPUException() ||
WritesToSystemRegister() || WritesToCoreRegister() ||
WritesToCPSR() || WritesToSystemRegister() ||
WritesToFPCR() || WritesToCPSR() ||
WritesToFPSR() || WritesToFPCR() ||
AltersExclusiveState() || WritesToFPSR() ||
IsMemoryWrite() || AltersExclusiveState() ||
IsMemoryWrite() ||
IsCoprocessorInstruction(); IsCoprocessorInstruction();
} }

17
tests/A64/a64.cpp
View file

@ -634,20 +634,3 @@ TEST_CASE("A64: Optimization failure when folding ADD", "[a64]") {
REQUIRE(jit.GetPstate() == 0x20000000); REQUIRE(jit.GetPstate() == 0x20000000);
REQUIRE(jit.GetVector(30) == Vector{0xf7f6f5f4, 0}); REQUIRE(jit.GetVector(30) == Vector{0xf7f6f5f4, 0});
} }
TEST_CASE("A64: IC", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0
env.code_mem.emplace_back(0x14000000); // B .
jit.SetRegister(0, 0);
jit.SetPC(0);
env.ticks_left = 2;
jit.Run();
REQUIRE(jit.GetRegister(0) == 0);
REQUIRE(jit.GetPC() == 4);
}