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asimd_one_reg_modified_immediate: Use {Get,Set}Vector

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This commit is contained in:
MerryMage 2020-05-28 20:40:26 +01:00
parent cae857b8c8
commit 7d0b16de32
1 changed files with 21 additions and 14 deletions
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35
src/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp
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@ -16,15 +16,16 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
return UndefinedInstruction(); return UndefinedInstruction();
} }
const auto d_reg = ToExtRegD(Vd, D); const auto d_reg = ToVector(Q, Vd, D);
const size_t regs = Q ? 2 : 1;
const auto imm = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h)); const auto imm = AdvSIMDExpandImm(op, cmode, concatenate(a, b, c, d, e, f, g, h));
// VMOV // VMOV
const auto mov = [&] { const auto mov = [&] {
const auto imm64 = ir.Imm64(imm); const auto imm64 = ir.Imm64(imm);
for (size_t i = 0; i < regs; i++) { if (Q) {
ir.SetExtendedRegister(d_reg + i, imm64); ir.SetVector(d_reg, ir.VectorBroadcast(64, imm64));
} else {
ir.SetExtendedRegister(d_reg, imm64);
} }
return true; return true;
}; };
@ -32,8 +33,10 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
// VMVN // VMVN
const auto mvn = [&] { const auto mvn = [&] {
const auto imm64 = ir.Imm64(~imm); const auto imm64 = ir.Imm64(~imm);
for (size_t i = 0; i < regs; i++) { if (Q) {
ir.SetExtendedRegister(d_reg + i, imm64); ir.SetVector(d_reg, ir.VectorBroadcast(64, imm64));
} else {
ir.SetExtendedRegister(d_reg, imm64);
} }
return true; return true;
}; };
@ -41,10 +44,12 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
// VORR // VORR
const auto orr = [&] { const auto orr = [&] {
const auto imm64 = ir.Imm64(imm); const auto imm64 = ir.Imm64(imm);
for (size_t i = 0; i < regs; i++) { if (Q) {
const auto d_index = d_reg + i; const auto reg_value = ir.GetVector(d_reg);
const auto reg_value = ir.GetExtendedRegister(d_index); ir.SetVector(d_reg, ir.VectorOr(reg_value, ir.VectorBroadcast(64, imm64)));
ir.SetExtendedRegister(d_index, ir.Or(reg_value, imm64)); } else {
const auto reg_value = ir.GetExtendedRegister(d_reg);
ir.SetExtendedRegister(d_reg, ir.Or(reg_value, imm64));
} }
return true; return true;
}; };
@ -52,10 +57,12 @@ bool ArmTranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c,
// VBIC // VBIC
const auto bic = [&] { const auto bic = [&] {
const auto imm64 = ir.Imm64(~imm); const auto imm64 = ir.Imm64(~imm);
for (size_t i = 0; i < regs; i++) { if (Q) {
const auto d_index = d_reg + i; const auto reg_value = ir.GetVector(d_reg);
const auto reg_value = ir.GetExtendedRegister(d_index); ir.SetVector(d_reg, ir.VectorAnd(reg_value, ir.VectorBroadcast(64, imm64)));
ir.SetExtendedRegister(d_index, ir.And(reg_value, imm64)); } else {
const auto reg_value = ir.GetExtendedRegister(d_reg);
ir.SetExtendedRegister(d_reg, ir.And(reg_value, imm64));
} }
return true; return true;
}; };