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A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)

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This commit is contained in:
MerryMage 2018-02-04 13:21:31 +00:00
parent 2409e5d082
commit 7e82d8eede
2 changed files with 56 additions and 2 deletions
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4
src/frontend/A64/decoder/a64.inc
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@ -893,8 +893,8 @@ INST(EOR_asimd, "EOR (vector)", "0Q101
// Data Processing - FP and SIMD - Conversion between floating point and integer // Data Processing - FP and SIMD - Conversion between floating point and integer
//INST(FCVTNS_float, "FCVTNS (scalar)", "z0011110yy100000000000nnnnnddddd") //INST(FCVTNS_float, "FCVTNS (scalar)", "z0011110yy100000000000nnnnnddddd")
//INST(FCVTNU_float, "FCVTNU (scalar)", "z0011110yy100001000000nnnnnddddd") //INST(FCVTNU_float, "FCVTNU (scalar)", "z0011110yy100001000000nnnnnddddd")
//INST(SCVTF_float_int, "SCVTF (scalar, integer)", "z0011110yy100010000000nnnnnddddd") INST(SCVTF_float_int, "SCVTF (scalar, integer)", "z0011110yy100010000000nnnnnddddd")
//INST(UCVTF_float_int, "UCVTF (scalar, integer)", "z0011110yy100011000000nnnnnddddd") INST(UCVTF_float_int, "UCVTF (scalar, integer)", "z0011110yy100011000000nnnnnddddd")
//INST(FCVTAS_float, "FCVTAS (scalar)", "z0011110yy100100000000nnnnnddddd") //INST(FCVTAS_float, "FCVTAS (scalar)", "z0011110yy100100000000nnnnnddddd")
//INST(FCVTAU_float, "FCVTAU (scalar)", "z0011110yy100101000000nnnnnddddd") //INST(FCVTAU_float, "FCVTAU (scalar)", "z0011110yy100101000000nnnnnddddd")
//INST(FMOV_float_gen, "FMOV (general)", "z0011110yy10-11-000000nnnnnddddd") //INST(FMOV_float_gen, "FMOV (general)", "z0011110yy10-11-000000nnnnnddddd")

54
src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
View file

@ -22,6 +22,60 @@ static boost::optional<size_t> GetDataSize(Imm<2> type) {
return boost::none; return boost::none;
} }
bool TranslatorVisitor::SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
const size_t intsize = sf ? 64 : 32;
const auto fltsize = GetDataSize(type);
if (!fltsize || *fltsize == 16) {
return UnallocatedEncoding();
}
const IR::U32U64 intval = X(intsize, Rn);
IR::U32U64 fltval;
if (intsize == 32 && *fltsize == 32) {
fltval = ir.FPS32ToSingle(intval, false, true);
} else if (intsize == 32 && *fltsize == 64) {
fltval = ir.FPS32ToDouble(intval, false, true);
} else if (intsize == 64 && *fltsize == 32) {
return InterpretThisInstruction();
} else if (intsize == 64 && *fltsize == 64) {
return InterpretThisInstruction();
} else {
UNREACHABLE();
}
V_scalar(*fltsize, Vd, fltval);
return true;
}
bool TranslatorVisitor::UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
const size_t intsize = sf ? 64 : 32;
const auto fltsize = GetDataSize(type);
if (!fltsize || *fltsize == 16) {
return UnallocatedEncoding();
}
const IR::U32U64 intval = X(intsize, Rn);
IR::U32U64 fltval;
if (intsize == 32 && *fltsize == 32) {
fltval = ir.FPU32ToSingle(intval, false, true);
} else if (intsize == 32 && *fltsize == 64) {
fltval = ir.FPU32ToDouble(intval, false, true);
} else if (intsize == 64 && *fltsize == 32) {
return InterpretThisInstruction();
} else if (intsize == 64 && *fltsize == 64) {
return InterpretThisInstruction();
} else {
UNREACHABLE();
}
V_scalar(*fltsize, Vd, fltval);
return true;
}
bool TranslatorVisitor::FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) { bool TranslatorVisitor::FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
const size_t intsize = sf ? 64 : 32; const size_t intsize = sf ? 64 : 32;
const auto fltsize = GetDataSize(type); const auto fltsize = GetDataSize(type);