test_generator: Test ASIMD
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2532cfba4d
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1 changed files with 16 additions and 2 deletions
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@ -61,6 +61,20 @@ bool ShouldTestInst(u32 instruction, u32 pc, bool is_thumb, bool is_last_inst, A
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case IR::Opcode::A32CoprocGetTwoWords:
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case IR::Opcode::A32CoprocLoadWords:
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case IR::Opcode::A32CoprocStoreWords:
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// Half-precision
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case IR::Opcode::FPVectorAbs16:
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case IR::Opcode::FPVectorEqual16:
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case IR::Opcode::FPVectorMulAdd16:
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case IR::Opcode::FPVectorNeg16:
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case IR::Opcode::FPVectorRecipEstimate16:
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case IR::Opcode::FPVectorRecipStepFused16:
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case IR::Opcode::FPVectorRoundInt16:
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case IR::Opcode::FPVectorRSqrtEstimate16:
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case IR::Opcode::FPVectorRSqrtStepFused16:
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case IR::Opcode::FPVectorToSignedFixed16:
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case IR::Opcode::FPVectorToUnsignedFixed16:
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case IR::Opcode::FPVectorFromHalf32:
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case IR::Opcode::FPVectorToHalf32:
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return false;
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default:
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continue;
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@ -78,7 +92,7 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
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const std::vector<std::tuple<std::string, const char*>> list{
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#define INST(fn, name, bitstring) {#fn, bitstring},
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#include "dynarmic/frontend/A32/decoder/arm.inc"
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//#include "dynarmic/frontend/A32/decoder/asimd.inc"
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#include "dynarmic/frontend/A32/decoder/asimd.inc"
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#include "dynarmic/frontend/A32/decoder/vfp.inc"
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#undef INST
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};
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@ -156,7 +170,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
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const std::vector<std::tuple<std::string, const char*>> asimd_list{
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#define INST(fn, name, bitstring) {#fn, bitstring},
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//#include "dynarmic/frontend/A32/decoder/asimd.inc"
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#include "dynarmic/frontend/A32/decoder/asimd.inc"
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#undef INST
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};
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